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soc/cores/spi_opi: documentation fixes 

The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2020-03-10 20:40:04 +08:00
parent d2f6139dc7
commit a2f61b4e80
1 changed files with 7 additions and 8 deletions
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15
litex/soc/cores/spi_opi.py
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@ -18,9 +18,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
sim = False, sim = False,
spiread = False, spiread = False,
prefetch_lines = 1): prefetch_lines = 1):
self.intro = ModuleDoc(""" self.intro = ModuleDoc("""Intro
Intro
********
SpiOpi implements a dual-mode SPI or OPI interface. OPI is an octal (8-bit) wide variant of SpiOpi implements a dual-mode SPI or OPI interface. OPI is an octal (8-bit) wide variant of
SPI, which is unique to Macronix parts. It is concurrently interoperable with SPI. The chip SPI, which is unique to Macronix parts. It is concurrently interoperable with SPI. The chip
@ -300,14 +298,13 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
), ),
] ]
self.architecture = ModuleDoc(""" self.architecture = ModuleDoc("""Architecture
Architecture
**************
The machine is split into two separate pieces, one to handle SPI, and one to handle OPI. The machine is split into two separate pieces, one to handle SPI, and one to handle OPI.
SPI SPI
===== -----
The SPI machine architecture is split into two levels: MAC and PHY. The SPI machine architecture is split into two levels: MAC and PHY.
The MAC layer is responsible for: The MAC layer is responsible for:
@ -333,7 +330,8 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
Thus holding "req" high can allow the PHY to back-to-back issue cycles without pause. Thus holding "req" high can allow the PHY to back-to-back issue cycles without pause.
OPI OPI
===== -----
The OPI machine is split into three parts: a command controller, a Tx PHY, and an Rx PHY. The OPI machine is split into three parts: a command controller, a Tx PHY, and an Rx PHY.
The Tx PHY is configured with a "dummy cycle" count register, as there is a variable length The Tx PHY is configured with a "dummy cycle" count register, as there is a variable length
@ -389,6 +387,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
- pre-fetch is aborted because bus_adr and next read address don't match and FIFO is reset - pre-fetch is aborted because bus_adr and next read address don't match and FIFO is reset
RxPHY: RxPHY:
- while CTI==2, assemble data into 32-bit words as soon as EMPTY is deasserted, - while CTI==2, assemble data into 32-bit words as soon as EMPTY is deasserted,
present a bus_ack, and increment the next read address pointer present a bus_ack, and increment the next read address pointer
- when CTI==7, ack the data, and wait until the next bus cycle with CTI==2 to resume - when CTI==7, ack the data, and wait until the next bus cycle with CTI==2 to resume