litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
This commit is contained in:
Florent Kermarrec
parent
d86db6f12b
commit
a3584147a5
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@ -68,80 +68,6 @@ class AXIInterface(Record):
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self.ar = stream.Endpoint(ax_description(address_width, id_width))
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self.ar = stream.Endpoint(ax_description(address_width, id_width))
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self.r = stream.Endpoint(r_description(data_width, id_width))
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self.r = stream.Endpoint(r_description(data_width, id_width))
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def _signals_in_channels(self, channels):
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for channel_name in channels:
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channel = getattr(self, channel_name)
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for signal in channel.layout:
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if signal[0] == 'param':
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continue
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if signal[0] == 'payload':
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for s in signal[1]:
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yield s[0], channel_name, s[1], s[2]
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else:
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if signal[0] == 'first':
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continue
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if signal[0] == 'last' and channel_name != 'w' and channel_name != 'r':
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continue
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yield signal[0], channel_name, signal[1], signal[2]
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def to_pads(self, bus_name='axi'):
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axi_bus = {}
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for signal, channel, width, direction in self._signals_in_channels(['aw', 'w', 'b', 'ar', 'r']):
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signal_name = channel + signal
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axi_bus[signal_name] = width
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signals = []
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for pad in axi_bus:
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signals.append(Subsignal(pad, Pins(axi_bus[pad])))
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pads = [
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(bus_name , 0) + tuple(signals)
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]
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return pads
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def connect_to_pads(self, module, platform, bus_name, mode='master'):
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def _get_signals(pads, channel, signal):
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signal_name = channel + signal
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channel = getattr(self, channel)
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axi_signal = getattr(channel, signal)
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pads_signal = getattr(pads, signal_name)
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return pads_signal, axi_signal
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axi_pads = self.to_pads(bus_name)
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platform.add_extension(axi_pads)
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pads = platform.request(bus_name)
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for signal, channel, width, direction in self._signals_in_channels(['aw', 'w', 'ar']):
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pads_signal, axi_signal = _get_signals(pads, channel, signal)
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if mode == 'master':
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if direction == DIR_M_TO_S:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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else:
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if direction == DIR_S_TO_M:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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for signal, channel, width, direction in self._signals_in_channels(['r', 'b']):
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pads_signal, axi_signal = _get_signals(pads, channel, signal)
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if mode == 'master':
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if direction == DIR_S_TO_M:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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else:
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if direction == DIR_M_TO_S:
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module.comb += pads_signal.eq(axi_signal)
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else:
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module.comb += axi_signal.eq(pads_signal)
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# AXI Lite Definition ------------------------------------------------------------------------------
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# AXI Lite Definition ------------------------------------------------------------------------------
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def ax_lite_description(address_width):
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def ax_lite_description(address_width):
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@ -174,6 +100,44 @@ class AXILiteInterface(Record):
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self.ar = stream.Endpoint(ax_lite_description(address_width))
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self.ar = stream.Endpoint(ax_lite_description(address_width))
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self.r = stream.Endpoint(r_lite_description(data_width))
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self.r = stream.Endpoint(r_lite_description(data_width))
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def get_ios(self, bus_name="wb"):
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subsignals = []
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for channel in ["aw", "w", "b", "ar", "r"]:
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for name in ["valid", "ready"]:
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subsignals.append(Subsignal(channel + name, Pins(1)))
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for name, width in getattr(self, channel).description.payload_layout:
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subsignals.append(Subsignal(channel + name, Pins(width)))
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ios = [(bus_name , 0) + tuple(subsignals)]
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return ios
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def connect_to_pads(self, pads, bus_name, mode="master"):
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assert mode in ["slave", "master"]
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r = []
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def swap_mode(mode): return "master" if mode == "slave" else "slave"
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channel_modes = {
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"aw": mode,
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"w" : mode,
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"b" : swap_mode(mode),
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"ar": mode,
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"r" : swap_mode(mode),
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}
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for channel, mode in channel_modes.items():
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for name, width in [("valid", 1)] + getattr(self, channel).description.payload_layout:
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sig = getattr(getattr(self, channel), name)
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pad = getattr(pads, channel + name)
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if mode == "master":
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r.append(pad.eq(sig))
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else:
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r.append(sig.eq(pad))
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for name, width in [("ready", 1)]:
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sig = getattr(getattr(self, channel), name)
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pad = getattr(pads, channel + name)
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if mode == "master":
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r.append(sig.eq(pad))
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else:
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r.append(pad.eq(sig))
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return r
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# AXI Bursts to Beats ------------------------------------------------------------------------------
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# AXI Bursts to Beats ------------------------------------------------------------------------------
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class AXIBurst2Beat(Module):
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class AXIBurst2Beat(Module):
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