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cpu/naxriscv: Generate CPU_MMU config based on xlen.

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Florent Kermarrec 2023-02-20 15:12:43 +01:00
parent 0f000a0a90
commit a3fbd9794c
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/cpu/naxriscv/core.py
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@ -302,7 +302,7 @@ class NaxRiscv(CPU):
# Define ISA. # Define ISA.
soc.add_config("CPU_ISA", NaxRiscv.get_arch()) soc.add_config("CPU_ISA", NaxRiscv.get_arch())
soc.add_config("CPU_MMU", "sv39") soc.add_config("CPU_MMU", {32 : "sv32", 64 : "sv39"}[NaxRiscv.xlen])
# Add PLIC Bus (AXILite Slave). # Add PLIC Bus (AXILite Slave).
self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32) self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32)