cpu/naxriscv: Generate CPU_MMU config based on xlen.
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@ -302,7 +302,7 @@ class NaxRiscv(CPU):
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# Define ISA.
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# Define ISA.
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soc.add_config("CPU_ISA", NaxRiscv.get_arch())
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soc.add_config("CPU_ISA", NaxRiscv.get_arch())
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soc.add_config("CPU_MMU", "sv39")
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soc.add_config("CPU_MMU", {32 : "sv32", 64 : "sv39"}[NaxRiscv.xlen])
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# Add PLIC Bus (AXILite Slave).
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# Add PLIC Bus (AXILite Slave).
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self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32)
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self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32)
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