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add SERV submodule

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This commit is contained in:
Florent Kermarrec 2019-09-28 00:41:28 +02:00
parent 49594ed7d4
commit a4069fc863
1 changed files with 3 additions and 0 deletions
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3
.gitmodules vendored
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@ -22,3 +22,6 @@
[submodule "litex/soc/cores/cpu/rocket/verilog"]
path = litex/soc/cores/cpu/rocket/verilog
url = https://github.com/enjoy-digital/rocket-litex-verilog
[submodule "litex/soc/cores/cpu/serv/verilog"]
path = litex/soc/cores/cpu/serv/verilog
url = https://github.com/olofk/serv