cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard).
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@ -20,13 +20,6 @@ import os
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class Open(Signal): pass
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = {
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"standard": "VexRiscv",
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"linux": "VexRiscv", # Similar to standard.
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}
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# VexRiscv SMP -------------------------------------------------------------------------------------
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class VexRiscvSMP(CPU):
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@ -34,7 +27,7 @@ class VexRiscvSMP(CPU):
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family = "riscv"
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name = "vexriscv"
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human_name = "VexRiscv SMP"
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variants = CPU_VARIANTS
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variants = ["standard", "linux"]
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data_width = 32
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV32
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@ -271,8 +264,8 @@ class VexRiscvSMP(CPU):
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def __init__(self, platform, variant):
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self.platform = platform
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self.variant = "standard"
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self.human_name = self.human_name + "-" + variant.upper()
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self.variant = "linux"
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self.human_name = self.human_name + "-" + self.variant.upper()
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self.reset = Signal()
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self.jtag_clk = Signal()
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self.jtag_enable = Signal()
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@ -33,9 +33,9 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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# Boot Arguments -------------------------------------------------------------------------------
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cpu_architectures = {
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"mor1kx": "or1k",
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"marocchino": "or1k",
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"vexriscv smp-linux": "riscv",
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"mor1kx" : "or1k",
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"marocchino" : "or1k",
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"vexriscv smp-linux" : "riscv",
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}
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default_initrd_start = {
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"or1k": 8*mB,
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