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cpu/vexriscv_smp/core: Only use Linux variant (Since similar to standard).

This commit is contained in:
Florent Kermarrec 2022-05-20 18:51:43 +02:00
parent 9ee9eb16a4
commit a426ec9e2f
2 changed files with 6 additions and 13 deletions
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13
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -20,13 +20,6 @@ import os
class Open(Signal): pass
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = {
"standard": "VexRiscv",
"linux": "VexRiscv", # Similar to standard.
}
# VexRiscv SMP -------------------------------------------------------------------------------------
class VexRiscvSMP(CPU):
@ -34,7 +27,7 @@ class VexRiscvSMP(CPU):
family = "riscv"
name = "vexriscv"
human_name = "VexRiscv SMP"
variants = CPU_VARIANTS
variants = ["standard", "linux"]
data_width = 32
endianness = "little"
gcc_triple = CPU_GCC_TRIPLE_RISCV32
@ -271,8 +264,8 @@ class VexRiscvSMP(CPU):
def __init__(self, platform, variant):
self.platform = platform
self.variant = "standard"
self.human_name = self.human_name + "-" + variant.upper()
self.variant = "linux"
self.human_name = self.human_name + "-" + self.variant.upper()
self.reset = Signal()
self.jtag_clk = Signal()
self.jtag_enable = Signal()

6
litex/tools/litex_json2dts_linux.py
View File

@ -33,9 +33,9 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Boot Arguments -------------------------------------------------------------------------------
cpu_architectures = {
"mor1kx": "or1k",
"marocchino": "or1k",
"vexriscv smp-linux": "riscv",
"mor1kx" : "or1k",
"marocchino" : "or1k",
"vexriscv smp-linux" : "riscv",
}
default_initrd_start = {
"or1k": 8*mB,