soc_sdram: update litedram
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@ -5,7 +5,6 @@ from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR
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from litex.soc.integration.soc_core import *
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from litedram.frontend import crossbar
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from litedram.frontend.wishbone import LiteDRAMWishbone2Native
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from litedram import dfii, core
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@ -27,7 +26,7 @@ class ControllerInjector(Module, AutoCSR):
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phy.settings, geom_settings, timing_settings, **kwargs)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
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self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface)
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class SoCSDRAM(SoCCore):
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