interconnect/wishbone: Add addressing parameter/property to allow Wishbone to use byte addressing (Currently using word addressing).
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@ -45,7 +45,7 @@ CTI_BURST_END = 0b111
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class Interface(Record):
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class Interface(Record):
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def __init__(self, data_width=32, adr_width=30, bursting=False, **kwargs):
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def __init__(self, data_width=32, adr_width=30, bursting=False, addressing="word", **kwargs):
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self.data_width = data_width
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self.data_width = data_width
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if kwargs.get("address_width", False):
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if kwargs.get("address_width", False):
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# FIXME: Improve or switch Wishbone to byte addressing instead of word addressing.
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# FIXME: Improve or switch Wishbone to byte addressing instead of word addressing.
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@ -53,10 +53,13 @@ class Interface(Record):
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self.adr_width = adr_width
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self.adr_width = adr_width
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self.address_width = adr_width + int(log2(data_width//8))
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self.address_width = adr_width + int(log2(data_width//8))
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self.bursting = bursting
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self.bursting = bursting
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assert addressing in ["word", "byte"]
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self.addressing = addressing
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Record.__init__(self, set_layout_parameters(_layout,
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Record.__init__(self, set_layout_parameters(_layout,
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adr_width = adr_width,
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adr_width = adr_width + (int(log2(data_width//8)) if (addressing == "byte") else 0),
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data_width = data_width,
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data_width = data_width,
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sel_width = data_width//8))
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sel_width = data_width//8,
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))
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self.adr.reset_less = True
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self.adr.reset_less = True
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self.dat_w.reset_less = True
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self.dat_w.reset_less = True
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self.dat_r.reset_less = True
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self.dat_r.reset_less = True
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@ -272,12 +275,16 @@ class DownConverter(Module):
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"""
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"""
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def __init__(self, master, slave):
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def __init__(self, master, slave):
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# Parameters/Checks.
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assert master.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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assert master.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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dw_from = len(master.dat_w)
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dw_from = len(master.dat_w)
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dw_to = len(slave.dat_w)
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dw_to = len(slave.dat_w)
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ratio = dw_from//dw_to
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ratio = dw_from//dw_to
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# # #
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# # #
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# Signals.
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skip = Signal()
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skip = Signal()
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done = Signal()
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done = Signal()
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count = Signal(max=ratio)
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count = Signal(max=ratio)
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@ -332,6 +339,9 @@ class DownConverter(Module):
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class UpConverter(Module):
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class UpConverter(Module):
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"""UpConverter"""
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"""UpConverter"""
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def __init__(self, master, slave):
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def __init__(self, master, slave):
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# Parameters/Checks.
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assert master.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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assert master.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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dw_from = len(master.dat_w)
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dw_from = len(master.dat_w)
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dw_to = len(slave.dat_w)
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dw_to = len(slave.dat_w)
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ratio = dw_to//dw_from
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ratio = dw_to//dw_from
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@ -359,17 +369,24 @@ class Converter(Module):
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def __init__(self, master, slave):
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def __init__(self, master, slave):
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self.master = master
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self.master = master
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self.slave = slave
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self.slave = slave
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assert master.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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assert master.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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# # #
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# # #
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# Signals.
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dw_from = len(master.dat_r)
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_r)
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dw_to = len(slave.dat_r)
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# DownConverter.
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if dw_from > dw_to:
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if dw_from > dw_to:
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downconverter = DownConverter(master, slave)
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downconverter = DownConverter(master, slave)
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self.submodules += downconverter
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self.submodules += downconverter
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# UpConverter.
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elif dw_from < dw_to:
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elif dw_from < dw_to:
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upconverter = UpConverter(master, slave)
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upconverter = UpConverter(master, slave)
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self.submodules += upconverter
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self.submodules += upconverter
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# Direct Connect.
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else:
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else:
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self.comb += master.connect(slave)
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self.comb += master.connect(slave)
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@ -379,6 +396,7 @@ class SRAM(Module):
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def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None):
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def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None):
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if bus is None:
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if bus is None:
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bus = Interface()
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bus = Interface()
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assert bus.addressing == "word" # FIXME: Test/Remove byte addressing limitation.
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self.bus = bus
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self.bus = bus
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bus_data_width = len(self.bus.dat_r)
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bus_data_width = len(self.bus.dat_r)
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if isinstance(mem_or_size, Memory):
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if isinstance(mem_or_size, Memory):
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@ -510,13 +528,18 @@ class Wishbone2CSR(Module):
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# # #
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# # #
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wishbone_adr_shift = {
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"word" : 0,
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"byte" : log2_int(self.wishbone.data_width//8),
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}[self.wishbone.addressing]
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# Registered Access.
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if register:
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if register:
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fsm = FSM(reset_state="IDLE")
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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fsm.act("IDLE",
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NextValue(self.csr.dat_w, self.wishbone.dat_w),
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NextValue(self.csr.dat_w, self.wishbone.dat_w),
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If(self.wishbone.cyc & self.wishbone.stb,
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If(self.wishbone.cyc & self.wishbone.stb,
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NextValue(self.csr.adr, self.wishbone.adr),
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NextValue(self.csr.adr, self.wishbone.adr[wishbone_adr_shift:]),
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NextValue(self.csr.we, self.wishbone.we & (self.wishbone.sel != 0)),
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NextValue(self.csr.we, self.wishbone.we & (self.wishbone.sel != 0)),
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NextState("WRITE-READ")
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NextState("WRITE-READ")
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)
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)
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@ -531,13 +554,13 @@ class Wishbone2CSR(Module):
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self.wishbone.dat_r.eq(self.csr.dat_r),
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self.wishbone.dat_r.eq(self.csr.dat_r),
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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# Un-Registered Access.
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else:
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else:
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fsm = FSM(reset_state="WRITE-READ")
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self.submodules.fsm = fsm = FSM(reset_state="WRITE-READ")
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self.submodules += fsm
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fsm.act("WRITE-READ",
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fsm.act("WRITE-READ",
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self.csr.dat_w.eq(self.wishbone.dat_w),
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self.csr.dat_w.eq(self.wishbone.dat_w),
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If(self.wishbone.cyc & self.wishbone.stb,
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If(self.wishbone.cyc & self.wishbone.stb,
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self.csr.adr.eq(self.wishbone.adr),
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self.csr.adr.eq(self.wishbone.adr[wishbone_adr_shift:]),
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self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
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self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
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NextState("ACK")
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NextState("ACK")
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)
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)
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