litecores: remove unneeded AutoCSR inheritance in example designs (thanks William D. Jones)

misoclib/com/liteeth/example_designs/targets/base.py

@@ -1,5 +1,4 @@
 from migen.bus import wishbone
-from migen.bank.description import *
 from migen.genlib.io import CRG
 from migen.fhdl.specials import Keep
 from mibuild.xilinx.vivado import XilinxVivadoToolchain
@@ -16,7 +15,7 @@ from misoclib.com.liteeth.phy import LiteEthPHY
 from misoclib.com.liteeth.core import LiteEthUDPIPCore
 
 
-class BaseSoC(SoC, AutoCSR):
+class BaseSoC(SoC):
     csr_map = {
         "phy":  11,
         "core": 12
@@ -62,7 +61,7 @@ set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
 """)
 
 
-class BaseSoCDevel(BaseSoC, AutoCSR):
+class BaseSoCDevel(BaseSoC):
     csr_map = {
         "la":            20
     }

misoclib/com/litepcie/example_designs/targets/dma.py

@@ -1,5 +1,4 @@
 from migen.bus import wishbone
-from migen.bank.description import *
 from migen.genlib.io import CRG
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.misc import timeline
@@ -39,7 +38,7 @@ class _CRG(Module, AutoCSR):
         self.sync += If(self._scratch.re, self._scratch.w.eq(self._scratch.r))
 
 
-class PCIeDMASoC(SoC, AutoCSR):
+class PCIeDMASoC(SoC):
     default_platform = "kc705"
     csr_map = {
         "crg":            16,

misoclib/com/liteusb/example_designs/targets/simple.py

@@ -1,4 +1,3 @@
-from migen.bank.description import *
 from migen.genlib.io import CRG
 from migen.actorlib.fifo import SyncFIFO
 
@@ -11,7 +10,7 @@ from misoclib.com.liteusb.frontend.wishbone import LiteUSBWishboneBridge
 
 from misoclib.com.gpio import GPIOOut
 
-class LiteUSBSoC(SoC, AutoCSR):
+class LiteUSBSoC(SoC):
     csr_map = {}
     csr_map.update(SoC.csr_map)
 

misoclib/mem/litesata/example_designs/targets/bist.py

@@ -1,7 +1,6 @@
 from misoclib.mem.litesata.common import *
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.bank.description import *
 
 from misoclib.soc import SoC
 
@@ -82,7 +81,7 @@ class StatusLeds(Module):
             self.comb += platform.request("user_led", 2*i+1).eq(sata_phy.ctrl.ready)
 
 
-class BISTSoC(SoC, AutoCSR):
+class BISTSoC(SoC):
     default_platform = "kc705"
     csr_map = {
         "sata_bist": 16
@@ -122,7 +121,7 @@ set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
 set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
 """)
 
-class BISTSoCDevel(BISTSoC, AutoCSR):
+class BISTSoCDevel(BISTSoC):
     csr_map = {
         "la": 17
     }

misoclib/mem/litesata/example_designs/targets/mirroring.py

@@ -1,7 +1,6 @@
 from misoclib.mem.litesata.common import *
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.bank.description import *
 
 from misoclib.soc import SoC
 
@@ -21,7 +20,7 @@ from misoclib.mem.litesata.frontend.bist import LiteSATABIST
 from misoclib.mem.litesata.example_designs.targets.bist import CRG, StatusLeds
 
 
-class MirroringSoC(SoC, AutoCSR):
+class MirroringSoC(SoC):
     default_platform = "kc705"
     csr_map = {
         "sata_bist0": 16,

misoclib/mem/litesata/example_designs/targets/striping.py

@@ -1,7 +1,6 @@
 from misoclib.mem.litesata.common import *
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.bank.description import *
 
 from misoclib.soc import SoC
 
@@ -21,7 +20,7 @@ from misoclib.mem.litesata.frontend.bist import LiteSATABIST
 from misoclib.mem.litesata.example_designs.targets.bist import CRG, StatusLeds
 
 
-class StripingSoC(SoC, AutoCSR):
+class StripingSoC(SoC):
     default_platform = "kc705"
     csr_map = {
         "sata_bist": 16
@@ -86,7 +85,7 @@ set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
            sata_tx_clk="sata_tx{}_clk".format(str(i))))
 
 
-class StripingSoCDevel(StripingSoC, AutoCSR):
+class StripingSoCDevel(StripingSoC):
     csr_map = {
         "la": 17
     }

misoclib/tools/litescope/example_designs/targets/simple.py

@@ -1,4 +1,3 @@
-from migen.bank.description import *
 from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
@@ -9,7 +8,7 @@ from misoclib.tools.litescope.frontend.la import LiteScopeLA
 
 from misoclib.com.uart.bridge import UARTWishboneBridge
 
-class LiteScopeSoC(SoC, AutoCSR):
+class LiteScopeSoC(SoC):
     csr_map = {
         "io":    16,
         "la":    17