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soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy

This commit is contained in:
Florent Kermarrec 2019-05-10 15:46:22 +02:00
parent 7445b9e2e0
commit a49d170a6d
1 changed files with 2 additions and 5 deletions
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7
litex/soc/integration/soc_sdram.py
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@ -62,13 +62,10 @@ class SoCSDRAM(SoCCore):
self.submodules.sdram = ControllerInjector( self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, **kwargs) phy, geom_settings, timing_settings, **kwargs)
dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2 # TODO: modify mem_map to allow larger memories.
sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +
geom_settings.colbits)*sdram_width//8 geom_settings.colbits)*phy.settings.databits//8
# TODO: modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024) main_ram_size = min(main_ram_size, 256*1024*1024)
self.add_constant("L2_SIZE", self.l2_size) self.add_constant("L2_SIZE", self.l2_size)