build/generic_toolchain: store fragment. Reorder build_io_constraints and build_timing_constraints
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@ -60,6 +60,7 @@ class GenericToolchain:
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self._build_dir = build_dir
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self._build_dir = build_dir
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self._synth_opts += synth_opts
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self._synth_opts += synth_opts
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self.platform = platform
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self.platform = platform
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self.fragment = fragment
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# Create Build Directory.
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# Create Build Directory.
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os.makedirs(self._build_dir, exist_ok=True)
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os.makedirs(self._build_dir, exist_ok=True)
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@ -67,12 +68,12 @@ class GenericToolchain:
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os.chdir(self._build_dir)
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os.chdir(self._build_dir)
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# Finalize Design.
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# Finalize Design.
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if not isinstance(fragment, _Fragment):
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if not isinstance(self.fragment, _Fragment):
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fragment = fragment.get_fragment()
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self.fragment = self.fragment.get_fragment()
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platform.finalize(fragment)
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platform.finalize(self.fragment)
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# Generate Verilog.
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# Generate Verilog.
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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v_output = platform.get_verilog(self.fragment, name=build_name, **kwargs)
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self._vns = v_output.ns
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self._vns = v_output.ns
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v_file = build_name + ".v"
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v_file = build_name + ".v"
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v_output.write(v_file)
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v_output.write(v_file)
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@ -84,12 +85,12 @@ class GenericToolchain:
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self.named_sc, self.named_pc = platform.resolve_signals(self._vns)
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self.named_sc, self.named_pc = platform.resolve_signals(self._vns)
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platform.add_source(v_file)
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platform.add_source(v_file)
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# Generate Design IO Constraints File.
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io_cst_file = self.build_io_constraints()
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# Generate Design Timing Constraints File.
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# Generate Design Timing Constraints File.
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tim_cst_file = self.build_timing_constraints(v_output.ns)
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tim_cst_file = self.build_timing_constraints(v_output.ns)
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# Generate Design IO Constraints File.
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io_cst_file = self.build_io_constraints()
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# Generate Design Placement Constraints File.
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# Generate Design Placement Constraints File.
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place_cst_file = self.build_placement_constraints()
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place_cst_file = self.build_placement_constraints()
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