Merge pull request #1691 from jersey99/clock-keep-optional

Clock keep optional for XilinxPlatform
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enjoy-digital 2023-05-17 16:36:47 +02:00 committed by GitHub
commit a4eac2d360
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2 changed files with 2 additions and 3 deletions

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@ -84,11 +84,11 @@ class XilinxPlatform(GenericPlatform):
def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs)
def add_period_constraint(self, clk, period):
def add_period_constraint(self, clk, period, keep=True):
if clk is None: return
if hasattr(clk, "p"):
clk = clk.p
self.toolchain.add_period_constraint(self, clk, period)
self.toolchain.add_period_constraint(self, clk, period, keep=keep)
def add_false_path_constraint(self, from_, to):
if hasattr(from_, "p"):

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@ -386,7 +386,6 @@ class XilinxVivadoToolchain(GenericToolchain):
if tools.subprocess_call_filtered(shell + [script], common.colors) != 0:
raise OSError("Error occured during Vivado's script execution.")
def vivado_build_args(parser):
toolchain_group = parser.add_argument_group(title="Vivado toolchain options")
toolchain_group.add_argument("--synth-mode", default="vivado", help="Synthesis mode (vivado or yosys).")