Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

uart: support async phys

This commit is contained in:
Robert Jordens 2015-07-19 01:23:35 -06:00 committed by Sebastien Bourdeauducq
parent 097248bce9
commit a501d7c52d
1 changed files with 19 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
misoclib/com/uart/__init__.py
View File

@ -2,14 +2,14 @@ from migen.fhdl.std import *
from migen.bank.description import * from migen.bank.description import *
from migen.bank.eventmanager import * from migen.bank.eventmanager import *
from migen.genlib.record import Record from migen.genlib.record import Record
from migen.flow.actor import Sink, Source from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
from migen.actorlib.fifo import SyncFIFO
class UART(Module, AutoCSR): class UART(Module, AutoCSR):
def __init__(self, phy, def __init__(self, phy,
tx_fifo_depth=16, tx_fifo_depth=16,
rx_fifo_depth=16): rx_fifo_depth=16,
phy_cd="sys"):
self._rxtx = CSR(8) self._rxtx = CSR(8)
self._txfull = CSRStatus() self._txfull = CSRStatus()
self._rxempty = CSRStatus() self._rxempty = CSRStatus()
@ -21,27 +21,30 @@ class UART(Module, AutoCSR):
# # # # # #
tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth) if phy_cd == "sys":
self.submodules += tx_fifo tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth)
rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth)
# Generate TX IRQ when tx_fifo becomes empty
tx_irq = tx_fifo.source.stb
else:
tx_fifo = ClockDomainsRenamer({"write": "sys", "read": phy_cd})(
AsyncFIFO([("data", 8)], tx_fifo_depth))
rx_fifo = ClockDomainsRenamer({"write": phy_cd, "read": "sys"})(
AsyncFIFO([("data", 8)], rx_fifo_depth))
# Generate TX IRQ when tx_fifo becomes non-full
tx_irq = ~tx_fifo.sink.ack
self.submodules += tx_fifo, rx_fifo
self.comb += [ self.comb += [
tx_fifo.sink.stb.eq(self._rxtx.re), tx_fifo.sink.stb.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r), tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ack), self._txfull.status.eq(~tx_fifo.sink.ack),
Record.connect(tx_fifo.source, phy.sink) Record.connect(tx_fifo.source, phy.sink),
] self.ev.tx.trigger.eq(tx_irq),
rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth)
self.submodules += rx_fifo
self.comb += [
Record.connect(phy.source, rx_fifo.sink), Record.connect(phy.source, rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.stb), self._rxempty.status.eq(~rx_fifo.source.stb),
self._rxtx.w.eq(rx_fifo.source.data), self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ack.eq(self.ev.rx.clear) rx_fifo.source.ack.eq(self.ev.rx.clear),
]
self.comb += [
# Generate TX IRQ when tx_fifo becomes empty
self.ev.tx.trigger.eq(tx_fifo.source.stb),
# Generate RX IRQ when rx_fifo becomes non-empty # Generate RX IRQ when rx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.stb), self.ev.rx.trigger.eq(~rx_fifo.source.stb),
] ]