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Merge pull request #178 from daveshah1/vexriscv_linux_yosys 

vexriscv: Fix some floating signals
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enjoy-digital 2019-05-04 20:02:42 +02:00 committed by GitHub
parent fcd518b5d0 a048ba47c4
commit a50aff2c74
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litex/soc/cores/cpu/vexriscv/core.py
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@ -126,6 +126,9 @@ class VexRiscv(Module, AutoCSR):
i_dBusWishbone_ERR=dbus.err) i_dBusWishbone_ERR=dbus.err)
if "linux" in variant: if "linux" in variant:
# Tie zero to prevent 1'bx here
self.cpu_params["i_softwareInterrupt"] = 0
self.cpu_params["i_externalInterruptS"] = 0
self.add_timer() self.add_timer()
if "debug" in variant: if "debug" in variant: