cpu/microwatt: Only add XICS for IRQ variants (fix standard variant).

2021-02-22 10:30:54 +01:00 · 2021-02-22 10:30:54 +01:00 · a51bf60712
parent d5c2f6760c
commit a51bf60712
1 changed files with 12 additions and 11 deletions
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@ -117,6 +117,7 @@ class Microwatt(CPU):
        assert reset_address == 0x00000000

    def add_soc_components(self, soc, soc_region_cls):
+        if "irq" in self.variant:
            self.submodules.xics = XICSSlave(
                platform     = self.platform,
                variant      = self.variant,