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cpu/microwatt: Only add XICS for IRQ variants (fix standard variant).

This commit is contained in:
Florent Kermarrec 2021-02-22 10:30:54 +01:00
parent d5c2f6760c
commit a51bf60712
1 changed files with 12 additions and 11 deletions
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23
litex/soc/cores/cpu/microwatt/core.py
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@ -117,17 +117,18 @@ class Microwatt(CPU):
assert reset_address == 0x00000000
def add_soc_components(self, soc, soc_region_cls):
self.submodules.xics = XICSSlave(
platform = self.platform,
variant = self.variant,
core_irq_out = self.core_ext_irq,
int_level_in = self.interrupt,
endianness = self.endianness
)
xicsicp_region = soc_region_cls(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False)
xicsics_region = soc_region_cls(origin=soc.mem_map.get("xicsics"), size=4096, cached=False)
soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)
if "irq" in self.variant:
self.submodules.xics = XICSSlave(
platform = self.platform,
variant = self.variant,
core_irq_out = self.core_ext_irq,
int_level_in = self.interrupt,
endianness = self.endianness
)
xicsicp_region = soc_region_cls(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False)
xicsics_region = soc_region_cls(origin=soc.mem_map.get("xicsics"), size=4096, cached=False)
soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)
@staticmethod
def add_sources(platform, use_ghdl_yosys_plugin=False):