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test/test_axi/test_axi_width_converter: Use address_width on Wishbone.Interface to simplify.

This commit is contained in:
Florent Kermarrec 2022-12-08 16:23:15 +01:00
parent fac9fb81a2
commit a54d5180ba
1 changed files with 5 additions and 8 deletions
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13
test/test_axi.py
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@ -340,11 +340,10 @@ class TestAXI(unittest.TestCase):
class DUT(Module): class DUT(Module):
def __init__(self, dw_from=64, dw_to=32): def __init__(self, dw_from=64, dw_to=32):
self.axi_master = axi_master = AXIInterface(data_width=dw_from) self.axi_master = axi_master = AXIInterface(data_width=dw_from)
self.axi_slave = axi_slave = AXIInterface(data_width=dw_to) self.axi_slave = axi_slave = AXIInterface(data_width=dw_to)
converter = AXIConverter(axi_master, axi_slave) converter = AXIConverter(axi_master, axi_slave)
self.submodules += converter self.submodules += converter
wb = wishbone.Interface(data_width=dw_to, wb = wishbone.Interface(data_width=dw_to, address_width=axi_slave.address_width)
adr_width=axi_slave.address_width - log2_int(axi_slave.data_width // 8))
axi2wb = AXI2Wishbone(axi_slave, wb) axi2wb = AXI2Wishbone(axi_slave, wb)
self.submodules += axi2wb self.submodules += axi2wb
self.mem = mem = wishbone.SRAM(1024, bus=wb, init=range(256)) self.mem = mem = wishbone.SRAM(1024, bus=wb, init=range(256))
@ -358,12 +357,10 @@ class TestAXI(unittest.TestCase):
""" """
def __init__(self, dw_from=64, dw_to=32): def __init__(self, dw_from=64, dw_to=32):
self.axi_master = axi_master = AXIInterface(data_width=dw_from) self.axi_master = axi_master = AXIInterface(data_width=dw_from)
wb_from = wishbone.Interface(data_width=dw_from, wb_from = wishbone.Interface(data_width=dw_from, address_width=axi_master.address_width)
adr_width=axi_master.address_width - log2_int(axi_master.data_width // 8))
axi2wb = AXI2Wishbone(axi_master, wb_from) axi2wb = AXI2Wishbone(axi_master, wb_from)
self.submodules += axi2wb self.submodules += axi2wb
wb_to = wishbone.Interface(data_width=dw_to, wb_to = wishbone.Interface(data_width=dw_to, address_width=axi_master.address_width)
adr_width=wb_from.adr_width - log2_int(wb_from.data_width // dw_to))
wb2wb = wishbone.Converter(wb_from, wb_to) wb2wb = wishbone.Converter(wb_from, wb_to)
self.submodules += wb2wb self.submodules += wb2wb
self.mem = mem = wishbone.SRAM(1024, bus=wb_to, init=range(256)) self.mem = mem = wishbone.SRAM(1024, bus=wb_to, init=range(256))
@ -418,4 +415,4 @@ class TestAXI(unittest.TestCase):
#dut = DUT(64, 32) #dut = DUT(64, 32)
dut = DUT_ref(64, 32) dut = DUT_ref(64, 32)
run_simulation(dut, [generator_rd(dut), generator_wr(dut)]) run_simulation(dut, [generator_rd(dut), generator_wr(dut)], vcd_name="sim.vcd")