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sdram/module: add AS4C16M16 for minispartan6

This commit is contained in:
Florent Kermarrec 2015-03-21 18:38:53 +01:00
parent 711540e15c
commit a560ba35bd
1 changed files with 18 additions and 0 deletions
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18
misoclib/mem/sdram/module.py
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@ -79,6 +79,24 @@ class MT48LC4M16(SDRAMModule):
SDRAMModule.__init__(self, clk_freq, self.geom_settings, SDRAMModule.__init__(self, clk_freq, self.geom_settings,
self.timing_settings) self.timing_settings)
class AS4C16M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 512
}
timing_settings = {
"tRP": 18,
"tRCD": 18,
"tWR": 12,
"tWTR": 2,
"tREFI": 256*1000*1000/4096,
"tRFC": 60
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
self.timing_settings)
# DDR # DDR
class MT46V32M16(SDRAMModule): class MT46V32M16(SDRAMModule):
geom_settings = { geom_settings = {