soc/interconnect/csr: Add optional support fixed CSR mapping.
By default, location is still automatically determined but it's now possible to
specific locations:
The following module:
class MyModule(Module, AutoCSR):
def __init__(self):
self.csr0 = CSRStorage()
self.csr1 = CSRStorage(n=0)
self.csr2 = CSRStorage(n=2)
built on a SoC with 32-bit CSR data-width will have the following CSR mapping:
- 0x00 : csr1
- 0x04 : csr0
- 0x08 : reserved
- 0x0c : csr2
This commit is contained in:
Florent Kermarrec
parent
804a1a5b26
commit
a57f0640cc
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@ -43,13 +43,14 @@ from migen.fhdl.tracer import get_obj_var_name
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# CSRBase ------------------------------------------------------------------------------------------
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class _CSRBase(DUID):
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def __init__(self, size, name):
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def __init__(self, size, name, n=None):
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DUID.__init__(self)
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self.n = n
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self.fixed = n is not None
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self.size = size
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self.name = get_obj_var_name(name)
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if self.name is None:
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raise ValueError("Cannot extract CSR name from code, need to specify.")
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self.size = size
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# CSRConstant --------------------------------------------------------------------------------------
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class CSRConstant(DUID):
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@ -59,8 +60,10 @@ class CSRConstant(DUID):
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running on the device.
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"""
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def __init__(self, value, bits_sign=None, name=None):
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def __init__(self, value, bits_sign=None, name=None, n=None):
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DUID.__init__(self)
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self.n = n
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self.fixed = n is not None
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self.value = Constant(value, bits_sign)
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self.name = get_obj_var_name(name)
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self.constant = value
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@ -105,8 +108,8 @@ class CSR(_CSRBase):
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It is active for one cycle, after or during a read from the bus.
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"""
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def __init__(self, size=1, name=None):
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_CSRBase.__init__(self, size, name)
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def __init__(self, size=1, name=None, n=None):
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_CSRBase.__init__(self, size, name, n)
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self.re = Signal(name=self.name + "_re")
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self.r = Signal(self.size, name=self.name + "_r")
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self.we = Signal(name=self.name + "_we")
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@ -129,8 +132,8 @@ class CSR(_CSRBase):
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class _CompoundCSR(_CSRBase, Module):
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def __init__(self, size, name):
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_CSRBase.__init__(self, size, name)
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def __init__(self, size, name, n=None):
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_CSRBase.__init__(self, size, name, n)
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self.simple_csrs = []
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def get_simple_csrs(self):
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@ -288,12 +291,12 @@ class CSRStatus(_CompoundCSR):
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The value of the CSRStatus register.
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"""
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def __init__(self, size=1, reset=0, fields=[], name=None, description=None, read_only=True):
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def __init__(self, size=1, reset=0, fields=[], name=None, description=None, read_only=True, n=None):
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if fields != []:
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self.fields = CSRFieldAggregate(fields, CSRAccess.ReadOnly)
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size = self.fields.get_size()
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reset = self.fields.get_reset()
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_CompoundCSR.__init__(self, size, name)
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_CompoundCSR.__init__(self, size, name, n)
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self.description = description
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self.read_only = read_only
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self.status = Signal(self.size, reset=reset)
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@ -377,12 +380,12 @@ class CSRStorage(_CompoundCSR):
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``write_from_dev == True``
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"""
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def __init__(self, size=1, reset=0, reset_less=False, fields=[], atomic_write=False, write_from_dev=False, name=None, description=None):
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def __init__(self, size=1, reset=0, reset_less=False, fields=[], atomic_write=False, write_from_dev=False, name=None, description=None, n=None):
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if fields != []:
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self.fields = CSRFieldAggregate(fields, CSRAccess.ReadWrite)
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size = self.fields.get_size()
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reset = self.fields.get_reset()
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_CompoundCSR.__init__(self, size, name)
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_CompoundCSR.__init__(self, size, name, n)
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self.description = description
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self.storage = Signal(self.size, reset=reset, reset_less=reset_less)
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self.atomic_write = atomic_write
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@ -460,6 +463,65 @@ def memprefix(prefix, memories, done):
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memory.name_override = prefix + memory.name_override
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done.add(memory.duid)
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def _sort_gathered_items(items):
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# Create list of variable items and sort it by DUID.
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# --------------------------------------------------
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variable_items = []
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for item in items:
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if not item.fixed:
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variable_items.append(item)
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variable_items = sorted(variable_items, key=lambda x: x.duid)
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# Create list of fixed items:
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# ---------------------------
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fixed_items = []
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for item in items:
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if item.fixed:
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fixed_items.append(item)
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# Determine items length.
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# -----------------------
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# Set to length of provided items.
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items_length = len(items)
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# Eventually extend with fixed items:
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for item in fixed_items:
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if item.n > items_length:
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items_length = (item.n + 1)
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# Create list of sorted items:
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# ----------------------------
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# Create empty list.
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sorted_items = [None for _ in range(items_length)]
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# Fill fixed items.
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for item in fixed_items:
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if sorted_items[item.n] is not None:
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csr0 = item.name
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csr1 = sorted_items[item.n].name
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raise ValueError(f"CSR conflict on location {item.n} between {csr0} and {csr1}.")
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sorted_items[item.n] = item
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# Fill variable items in empty locations.
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while len(variable_items):
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item = variable_items.pop(0)
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for i in range(items_length):
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if sorted_items[i] is None:
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sorted_items[i] = item
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break
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# Fill remaining location with reserved CSR.
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for i in range(items_length):
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if sorted_items[i] is None:
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sorted_items[i] = CSR(name=f"reserved{i}")
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# Verify all locations are filled.
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assert None not in sorted_items
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# Return.
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return sorted_items
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def _make_gatherer(method, cls, prefix_cb):
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def gatherer(self):
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@ -480,7 +542,7 @@ def _make_gatherer(method, cls, prefix_cb):
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items = getattr(v, method)()
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prefix_cb(k + "_", items, prefixed)
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r += items
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return sorted(r, key=lambda x: x.duid)
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return _sort_gathered_items(r)
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return gatherer
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@ -494,9 +556,9 @@ class AutoCSR:
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they will be called by the``AutoCSR`` methods and their CSR and memories added to the lists returned,
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with the child objects' names as prefixes.
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"""
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get_memories = _make_gatherer("get_memories", Memory, memprefix)
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get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)
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get_constants = _make_gatherer("get_constants", CSRConstant, csrprefix)
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get_memories = _make_gatherer(method="get_memories", cls=Memory, prefix_cb=memprefix)
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get_csrs = _make_gatherer(method="get_csrs", cls=_CSRBase, prefix_cb=csrprefix)
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get_constants = _make_gatherer(method="get_constants", cls=CSRConstant, prefix_cb=csrprefix)
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class GenericBank(Module):
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@ -508,7 +570,7 @@ class GenericBank(Module):
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if isinstance(c, CSR):
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assert c.size <= busword
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self.simple_csrs.append(c)
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else:
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elif hasattr(c, "finalize"):
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c.finalize(busword, ordering)
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self.simple_csrs += c.get_simple_csrs()
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self.submodules += c
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@ -215,14 +215,21 @@ class CSRBankArray(Module):
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self.scan(ifargs, ifkwargs)
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def scan(self, ifargs, ifkwargs):
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self.banks = []
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self.srams = []
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self.banks = []
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self.srams = []
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self.constants = []
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for name, obj in xdir(self.source, True):
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# Collect CSR Registers.
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# ---------------------
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csrs = []
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if hasattr(obj, "get_csrs"):
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csrs = obj.get_csrs()
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else:
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csrs = []
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# Collect CSR Memories.
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# ---------------------
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if hasattr(obj, "get_memories"):
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memories = obj.get_memories()
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for memory in memories:
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@ -241,9 +248,15 @@ class CSRBankArray(Module):
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self.submodules += mmap
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csrs += mmap.get_csrs()
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self.srams.append((name, memory, mapaddr, mmap))
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# Collect CSR Constants.
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# ----------------------
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if hasattr(obj, "get_constants"):
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for constant in obj.get_constants():
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self.constants.append((name, constant))
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# Create CSRBank with CSRs found.
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# -------------------------------
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if csrs:
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mapaddr = self.address_map(name, None)
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if mapaddr is None:
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@ -34,8 +34,8 @@ class CSRModule(Module, csr.AutoCSR):
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# # #
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# When csr is written:
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# - set storage to 0xdeadbeef
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# - set status to storage value
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# - Set storage to 0xdeadbeef.
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# - Set status to storage value.
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self.comb += [
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If(self._csr.re,
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self._storage.we.eq(1),
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@ -55,11 +55,15 @@ class CSRDUT(Module):
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def __init__(self):
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self.csr = csr_bus.Interface()
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self.submodules.csrmodule = CSRModule()
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self.submodules.csrmodule = CSRModule()
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self.submodules.csrbankarray = csr_bus.CSRBankArray(
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self, self.address_map)
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source = self,
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address_map = self.address_map,
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)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.csr, self.csrbankarray.get_buses())
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master = self.csr,
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slaves = self.csrbankarray.get_buses()
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)
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class TestCSR(unittest.TestCase):
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def test_csr_constant(self):
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