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test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.

This commit is contained in:
Florent Kermarrec 2020-08-04 09:37:53 +02:00
parent eb3374d00a
commit a5d0a340c3
3 changed files with 7 additions and 8 deletions
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6
litex/soc/interconnect/axi.py
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@ -496,8 +496,7 @@ class AXILite2Wishbone(Module):
def __init__(self, axi_lite, wishbone, base_address=0x00000000): def __init__(self, axi_lite, wishbone, base_address=0x00000000):
wishbone_adr_shift = log2_int(axi_lite.data_width//8) wishbone_adr_shift = log2_int(axi_lite.data_width//8)
assert axi_lite.data_width == len(wishbone.dat_r) assert axi_lite.data_width == len(wishbone.dat_r)
assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift, "axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift) assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift
print("####\n#### axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};\n####".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift))
_data = Signal(axi_lite.data_width) _data = Signal(axi_lite.data_width)
_r_addr = Signal(axi_lite.address_width) _r_addr = Signal(axi_lite.address_width)
@ -581,8 +580,7 @@ class Wishbone2AXILite(Module):
def __init__(self, wishbone, axi_lite, base_address=0x00000000): def __init__(self, wishbone, axi_lite, base_address=0x00000000):
wishbone_adr_shift = log2_int(axi_lite.data_width//8) wishbone_adr_shift = log2_int(axi_lite.data_width//8)
assert axi_lite.data_width == len(wishbone.dat_r) assert axi_lite.data_width == len(wishbone.dat_r)
assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift, "axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift) assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift
print("####\n#### axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};\n####".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift))
_cmd_done = Signal() _cmd_done = Signal()
_data_done = Signal() _data_done = Signal()

2
test/test_axi.py
View File

@ -237,7 +237,7 @@ class TestAXI(unittest.TestCase):
class DUT(Module): class DUT(Module):
def __init__(self): def __init__(self):
self.axi = AXIInterface(data_width=32, address_width=32, id_width=8) self.axi = AXIInterface(data_width=32, address_width=32, id_width=8)
self.wishbone = wishbone.Interface(data_width=32) self.wishbone = wishbone.Interface(data_width=32, adr_width=30)
axi2wishbone = AXI2Wishbone(self.axi, self.wishbone) axi2wishbone = AXI2Wishbone(self.axi, self.wishbone)
self.submodules += axi2wishbone self.submodules += axi2wishbone

7
test/test_axi_lite.py
View File

@ -146,12 +146,12 @@ class TestAXILite(unittest.TestCase):
def test_wishbone2axi2wishbone(self): def test_wishbone2axi2wishbone(self):
class DUT(Module): class DUT(Module):
def __init__(self): def __init__(self):
self.wishbone = wishbone.Interface(data_width=32) self.wishbone = wishbone.Interface(data_width=32, adr_width=30)
# # # # # #
axi = AXILiteInterface(data_width=32, address_width=32) axi = AXILiteInterface(data_width=32, address_width=32)
wb = wishbone.Interface(data_width=32) wb = wishbone.Interface(data_width=32, adr_width=30)
wishbone2axi = Wishbone2AXILite(self.wishbone, axi) wishbone2axi = Wishbone2AXILite(self.wishbone, axi)
axi2wishbone = AXILite2Wishbone(axi, wb) axi2wishbone = AXILite2Wishbone(axi, wb)
@ -190,7 +190,8 @@ class TestAXILite(unittest.TestCase):
"axi_lite": (AXILiteInterface, AXI2AXILite, AXILiteSRAM), "axi_lite": (AXILiteInterface, AXI2AXILite, AXILiteSRAM),
}[mem_bus] }[mem_bus]
bus = interface_cls() bus_kwargs = {"adr_width" : 30} if mem_bus == "wishbone" else {}
bus = interface_cls(**bus_kwargs)
self.submodules += converter_cls(axi, bus) self.submodules += converter_cls(axi, bus)
sram = sram_cls(1024, init=[0x12345678, 0xa55aa55a]) sram = sram_cls(1024, init=[0x12345678, 0xa55aa55a])
self.submodules += sram self.submodules += sram