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more understandable error when missing a memory

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Daniel Kucera 2019-08-13 10:14:16 +02:00 committed by GitHub
parent 2b815f7096
commit a5eaf172c5
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1 changed files with 1 additions and 1 deletions
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litex/soc/integration/soc_core.py
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@ -501,7 +501,7 @@ class SoCCore(Module):
if self.cpu_type is not None: if self.cpu_type is not None:
for mem in "rom", "sram": for mem in "rom", "sram":
if mem not in registered_mems: if mem not in registered_mems:
raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem)) raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem))
# Add the Wishbone Masters/Slaves interconnect # Add the Wishbone Masters/Slaves interconnect
if len(self._wb_masters): if len(self._wb_masters):