liteusb: add ft2232h_sync_tb
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from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.fhdl.specials import *
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from migen.sim.generic import run_simulation
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from misoclib.com.liteusb.common import *
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from misoclib.com.liteusb.phy.ft2232h import FT2232HPHYSynchronous
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from misoclib.com.liteusb.test.common import *
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# XXX for now use it from liteeth to avoid duplication
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from misoclib.com.liteeth.test.common import *
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class FT2232HSynchronousModel(Module, RandRun):
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def __init__(self, rd_data):
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RandRun.__init__(self, 10)
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self.rd_data = [0] + rd_data
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self.rd_idx = 0
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# pads
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self.data = Signal(8)
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self.rxf_n = Signal(reset=1)
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self.txe_n = Signal(reset=1)
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self.rd_n = Signal(reset=1)
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self.wr_n = Signal(reset=1)
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self.oe_n = Signal(reset=1)
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self.siwua = Signal()
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self.pwren_n = Signal(reset=1)
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self.init = True
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self.wr_data = []
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self.wait_wr_n = False
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self.rd_done = 0
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self.data_w = Signal(8)
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self.data_r = Signal(8)
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self.specials += Tristate(self.data, self.data_r, ~self.oe_n, self.data_w)
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def wr_sim(self, selfp):
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if not selfp.wr_n and not selfp.txe_n:
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self.wr_data.append(selfp.data_w)
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self.wait_wr_n = False
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if not self.wait_wr_n:
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if self.run:
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selfp.txe_n = 1
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else:
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if selfp.txe_n:
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self.wait_wr_n = True
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selfp.txe_n = 0
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def rd_sim(self, selfp):
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rxf_n = selfp.rxf_n
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if self.run:
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if self.rd_idx < len(self.rd_data)-1:
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self.rd_done = selfp.rxf_n
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selfp.rxf_n = 0
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else:
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selfp.rxf_n = self.rd_done
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else:
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selfp.rxf_n = self.rd_done
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if not selfp.rd_n and not selfp.oe_n:
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if self.rd_idx < len(self.rd_data)-1:
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self.rd_idx += not rxf_n
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selfp.data_r = self.rd_data[self.rd_idx]
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self.rd_done = 1
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def do_simulation(self, selfp):
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RandRun.do_simulation(self, selfp)
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if self.init:
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selfp.rxf_n = 0
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self.wr_data = []
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self.init = False
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self.wr_sim(selfp)
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self.rd_sim(selfp)
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test_packet = [i%256 for i in range(512)]
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class TB(Module):
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def __init__(self):
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self.submodules.model = FT2232HSynchronousModel(test_packet)
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self.submodules.phy = FT2232HPHYSynchronous(self.model)
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self.submodules.streamer = PacketStreamer(phy_description(8))
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self.submodules.streamer_randomizer = AckRandomizer(phy_description(8), level=10)
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self.submodules.logger_randomizer = AckRandomizer(phy_description(8), level=10)
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self.submodules.logger = PacketLogger(phy_description(8))
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self.comb += [
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Record.connect(self.streamer.source, self.streamer_randomizer.sink),
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self.phy.sink.stb.eq(self.streamer_randomizer.source.stb),
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self.phy.sink.data.eq(self.streamer_randomizer.source.data),
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self.streamer_randomizer.source.ack.eq(self.phy.sink.ack),
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self.logger_randomizer.sink.stb.eq(self.phy.source.stb),
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self.logger_randomizer.sink.data.eq(self.phy.source.data),
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self.phy.source.ack.eq(self.logger_randomizer.sink.ack),
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Record.connect(self.logger_randomizer.source, self.logger.sink)
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]
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# Use sys_clk as ftdi_clk in simulation
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self.comb += [
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ClockSignal("ftdi").eq(ClockSignal()),
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ResetSignal("ftdi").eq(ResetSignal())
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]
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def gen_simulation(self, selfp):
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yield from self.streamer.send(Packet(test_packet))
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for i in range(2000):
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yield
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s, l, e = check(test_packet, self.model.wr_data)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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s, l, e = check(test_packet, self.logger.packet[1:])
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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def main():
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run_simulation(TB(), ncycles=8000, vcd_name="my.vcd", keep_files=True)
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if __name__ == "__main__":
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main()
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