gen/common: Introduce LiteXModule class to simplify Modules creation and avoid common mistakes.
LiteXModule can be used as a remplacement of Migen's Module and in this initial version: - Automatically inherit from AutoCSR (Forgeting to inherit from AutoCSR on a Module was a common mistake). - Simplify design creation with: - m.module_x = .. equivalent of Migen's m.submodules.module_x = .. - m.special_x = .. equivalent of Migen's m.specials.special_x = .. - m.cd_x = .. equivalent of Migen's m.clock_domains.cd_x = .. - m += module_x equivalent of Migen's m.submodules += module_x. - m += special_x equivalent of Migen's m.specials += special_x. - m += cd_x equivalent of Migen's m.clock_domains += cd_x. -> Forgeting to attach a correctly a Sub-module/Special was a very common mistake and having to use m.submodules., m.specials., m.clock_domains. was not natural.
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@ -1,11 +1,16 @@
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#
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#
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# This file is part of LiteX.
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# This file is part of LiteX.
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#
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#
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# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen import *
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from migen.fhdl.module import _ModuleProxy
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from migen.fhdl.specials import Special
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from litex.soc.interconnect.csr import AutoCSR
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# Bit/Bytes Reversing ------------------------------------------------------------------------------
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def reverse_bits(s):
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def reverse_bits(s):
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return s[::-1]
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return s[::-1]
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@ -15,3 +20,42 @@ def reverse_bytes(s):
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n = (len(s) + 7)//8
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n = (len(s) + 7)//8
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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for i in reversed(range(n))])
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for i in reversed(range(n))])
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# LiteX Module -------------------------------------------------------------------------------------
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class LiteXModule(Module, AutoCSR):
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def __setattr__(m, name, value):
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# Migen:
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if name in ["comb", "sync", "specials", "submodules", "clock_domains"]:
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if not isinstance(value, _ModuleProxy):
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raise AttributeError("Attempted to assign special Module property - use += instead")
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# LiteX fix-up: Automatically collect specials/submodules/clock_domains:
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# - m.module_x = .. equivalent of Migen's m.submodules.module_x = ..
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elif isinstance(value, Module) and ((name, value) not in m._submodules):
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setattr(m.submodules, name, value)
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# - m.special_x = .. equivalent of Migen's m.specials.special_x = ..
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elif isinstance(value, Special) and (value not in m._fragment.specials):
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setattr(m.specials, name, value)
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# - m.cd_x = .. equivalent of Migen's m.clock_domains.cd_x = ..
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elif isinstance(value, ClockDomain) and (value not in m._fragment.clock_domains):
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setattr(m.clock_domains, name, value)
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# Else use default __setattr__.
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else:
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object.__setattr__(m, name, value)
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# LiteX fix-up: Automatically collect specials/submodules/clock_domains:
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def __iadd__(m, other):
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# - m += module_x equivalent of Migen's m.submodules += module_x.
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if isinstance(other, Module):
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print(other)
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m.submodules += other
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# - m += special_x equivalent of Migen's m.specials += special_x.
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elif isinstnace(other, Special):
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m.specials += other
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# - m += cd_x equivalent of Migen's m.clock_domains += cd_x.
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elif isinstance(other, ClockDomain):
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m.clock_domains += other
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# Else use default __iadd__.
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else:
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object.__iadd__(m, other)
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return m
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@ -15,6 +15,7 @@ import datetime
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from math import log2, ceil
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from math import log2, ceil
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from migen import *
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from migen import *
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from litex.gen import LiteXModule
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from litex.soc.cores import cpu
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from litex.soc.cores import cpu
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@ -766,7 +767,7 @@ class SoCController(Module, AutoCSR):
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# SoC ----------------------------------------------------------------------------------------------
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# SoC ----------------------------------------------------------------------------------------------
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class SoC(Module):
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class SoC(LiteXModule):
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mem_map = {}
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mem_map = {}
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def __init__(self, platform, sys_clk_freq,
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def __init__(self, platform, sys_clk_freq,
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bus_standard = "wishbone",
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bus_standard = "wishbone",
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