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soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing

This commit is contained in:
Florent Kermarrec 2019-11-01 09:23:42 +01:00
parent 855d0e925d
commit a762d29b19
2 changed files with 5 additions and 2 deletions
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1
litex/build/generic_platform.py
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@ -268,6 +268,7 @@ class GenericPlatform:
self.name = name self.name = name
self.sources = [] self.sources = []
self.verilog_include_paths = [] self.verilog_include_paths = []
self.output_dir = None
self.finalized = False self.finalized = False
def request(self, *args, **kwargs): def request(self, *args, **kwargs):

6
litex/soc/integration/builder.py
View File

@ -160,9 +160,11 @@ class Builder:
self.soc.initialize_rom(bios_data) self.soc.initialize_rom(bios_data)
def build(self, toolchain_path=None, **kwargs): def build(self, toolchain_path=None, **kwargs):
self.soc.finalize() self.soc.platform.output_dir = self.output_dir
os.makedirs(os.path.join(self.output_dir, "gateware"), exist_ok=True)
os.makedirs(os.path.join(self.output_dir, "software"), exist_ok=True)
os.makedirs(self.output_dir, exist_ok=True) self.soc.finalize()
self._generate_includes() self._generate_includes()
if self.soc.cpu_type is not None: if self.soc.cpu_type is not None: