soc/builder: add initialize_memory()
Allows the target soc to override memory initialization: rom and/or ram.
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@ -388,8 +388,11 @@ class Builder:
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self._prepare_rom_software()
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self._prepare_rom_software()
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self._generate_rom_software(compile_bios=use_bios)
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self._generate_rom_software(compile_bios=use_bios)
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# Allow soc to override the memory initialisation.
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self.soc.initialize_memory(self.software_dir, **kwargs)
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# Initialize ROM.
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# Initialize ROM.
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if use_bios and self.soc.integrated_rom_size:
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if use_bios and self.soc.integrated_rom_size and not getattr(self.soc, "rom").mem.init:
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self._initialize_rom_software()
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self._initialize_rom_software()
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# Translate compile_gateware to run.
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# Translate compile_gateware to run.
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@ -282,6 +282,48 @@ class SoCCore(LiteXSoC):
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def add_csr_region(self, name, origin, busword, obj):
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def add_csr_region(self, name, origin, busword, obj):
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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def initialize_memory(self, software_dir, **kwargs):
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"""initialize_memory
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The target SoC can implement this function to override the memory initialisation
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during the build to load a program or data to main_ram and/or rom.
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Parameters
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----------
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software_dir : str
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Builder software_dir where the soc libs and bios are built.
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kwargs
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Builder kwargs for any additional context if required
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.
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Example:
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class MySoC(SoCCore):
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def __init__(self,
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...
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self.add_config("MAIN_RAM_INIT") # firmware is in ram
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def initialize_memory(self, software_dir, **kwargs):
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if self.cpu_type is None:
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return
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filename = os.path.join(software_dir, "firmware", "firmware.bin")
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data = get_mem_data(filename, endianness=self.cpu.endianness)
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self.init_rom(name="main_ram", contents=data, auto_size=False)
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def main():
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...
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builder = Builder(soc, **parser.builder_argdict)
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# add custom firmware: compiled by connecting here and stored in initialize_memory()
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src="firmware"
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src_dir = os.path.join(os.path.abspath(os.path.dirname(__file__)), src)
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builder.add_software_package(src, src_dir)
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builder.build(**parser.toolchain_argdict)
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"""
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pass
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# SoCCore arguments --------------------------------------------------------------------------------
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# SoCCore arguments --------------------------------------------------------------------------------
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def soc_core_args(parser):
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def soc_core_args(parser):
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