Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)

This commit is contained in:
Florent Kermarrec 2019-04-19 09:18:25 +02:00
parent a92e90b215
commit a78ca2de92
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/build/xilinx/vivado.py
View File

@ -1,4 +1,4 @@
# This file is Copyright (c) 2014 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD # License: BSD
import os import os
@ -118,6 +118,7 @@ class XilinxVivadoToolchain:
for filename, language, library in sources: for filename, language, library in sources:
filename_tcl = "{" + filename + "}" filename_tcl = "{" + filename + "}"
tcl.append("add_files " + filename_tcl) tcl.append("add_files " + filename_tcl)
if language == "vhdl":
tcl.append("set_property library {} [get_files {}]" tcl.append("set_property library {} [get_files {}]"
.format(library, filename_tcl)) .format(library, filename_tcl))
for filename in edifs: for filename in edifs: