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Fix missing include in ibex 

Change Ibex to use pythondata-cpu-ibex package and also fix the error of missing include by adding the dependency files first to the list of source files. As mentioned in  lowRISC/ibex#1461.
This commit is contained in:
Navaneeth Bhardwaj 2021-10-20 18:26:02 +05:30
parent cf2e073b14
commit a7a746473d
1 changed files with 14 additions and 21 deletions
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35
litex/soc/cores/cpu/ibex/core.py
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@ -190,6 +190,19 @@ class Ibex(CPU):
@staticmethod @staticmethod
def add_sources(platform): def add_sources(platform):
ibexdir = get_data_mod("cpu", "ibex").data_location ibexdir = get_data_mod("cpu", "ibex").data_location
platform.add_verilog_include_path(os.path.join(ibexdir, "rtl"))
platform.add_verilog_include_path(os.path.join(ibexdir,
"vendor", "lowrisc_ip", "dv", "sv", "dv_utils")
)
platform.add_verilog_include_path(os.path.join(ibexdir,
"vendor", "lowrisc_ip", "ip", "prim", "rtl")
)
platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"),
"prim_alert_pkg.sv",
"prim_assert.sv",
"prim_ram_1p_pkg.sv",
)
platform.add_sources(os.path.join(ibexdir, "rtl"), platform.add_sources(os.path.join(ibexdir, "rtl"),
"ibex_pkg.sv", "ibex_pkg.sv",
"ibex_alu.sv", "ibex_alu.sv",
@ -210,27 +223,7 @@ class Ibex(CPU):
"ibex_register_file_fpga.sv", "ibex_register_file_fpga.sv",
"ibex_wb_stage.sv", "ibex_wb_stage.sv",
"ibex_core.sv", "ibex_core.sv",
#"ibex_top.sv" FIXME. "ibex_top.sv"
)
# FIXME: Patch ibex_top.sv to fix missing import.
if not os.path.exists("ibex_top.sv"):
# Get ibex_top source.
os.system("cp {src} {dst}".format(src=os.path.join(ibexdir, "rtl", "ibex_top.sv"), dst="ibex_top.sv"))
# FIXME: Patch ibex_top
os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/ibex_top.patch")
platform.add_source("ibex_top.sv")
platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"),
"prim_alert_pkg.sv",
"prim_assert.sv"
)
platform.add_verilog_include_path(os.path.join(ibexdir, "rtl"))
platform.add_verilog_include_path(os.path.join(ibexdir,
"vendor", "lowrisc_ip", "dv", "sv", "dv_utils")
)
platform.add_verilog_include_path(os.path.join(ibexdir,
"vendor", "lowrisc_ip", "ip", "prim", "rtl")
) )
def set_reset_address(self, reset_address): def set_reset_address(self, reset_address):