sdramphy/initsequence: cleanup and expose DDR3 MR1 value
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114890ee80
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@ -66,22 +66,6 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
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"CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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"CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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}
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}
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def gen_cmd(comment, a, ba, cmd, delay):
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r = "\t/* {0} */\n".format(comment)
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r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
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r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
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if cmd[:12] == "DFII_CONTROL":
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r += "\tdfii_control_write({0});\n".format(cmd)
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else:
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r += "\tcommand_p0({0});\n".format(cmd)
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if delay:
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r += "\tcdelay({0:d});\n".format(delay)
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r += "\n"
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return r
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r += "static void init_sequence(void)\n{\n"
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cl = sdram_phy.phy_settings.cl
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cl = sdram_phy.phy_settings.cl
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if sdram_phy.phy_settings.memtype == "SDR":
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if sdram_phy.phy_settings.memtype == "SDR":
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@ -136,7 +120,7 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
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elif sdram_phy.phy_settings.memtype == "DDR2":
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elif sdram_phy.phy_settings.memtype == "DDR2":
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bl = 2*sdram_phy.phy_settings.nphases
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bl = 2*sdram_phy.phy_settings.nphases
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wr = 2
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wr = 2
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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emr = 0
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emr = 0
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emr2 = 0
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emr2 = 0
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emr3 = 0
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emr3 = 0
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@ -218,13 +202,26 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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]
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# the value of MR1 needs to be modified during write leveling
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r += "#define DDR3_MR1 {}\n\n".format(mr1)
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else:
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else:
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raise NotImplementedError("Unsupported memory type: "+sdram_phy.phy_settings.memtype)
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raise NotImplementedError("Unsupported memory type: "+sdram_phy.phy_settings.memtype)
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r += "static void init_sequence(void)\n{\n"
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for comment, a, ba, cmd, delay in init_sequence:
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for comment, a, ba, cmd, delay in init_sequence:
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r += gen_cmd(comment, a, ba, cmd, delay)
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r += "\t/* {0} */\n".format(comment)
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r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
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r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
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if cmd[:12] == "DFII_CONTROL":
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r += "\tdfii_control_write({0});\n".format(cmd)
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else:
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r += "\tcommand_p0({0});\n".format(cmd)
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if delay:
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r += "\tcdelay({0:d});\n".format(delay)
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r += "\n"
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r += "}\n"
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r += "}\n"
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r += "#endif\n"
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r += "#endif\n"
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return r
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return r
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