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sdramphy/initsequence: cleanup and expose DDR3 MR1 value

This commit is contained in:
Sebastien Bourdeauducq 2014-09-03 14:21:30 +08:00
parent 114890ee80
commit a7b4550e59
1 changed files with 16 additions and 19 deletions
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33
misoclib/sdramphy/initsequence.py
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@ -66,22 +66,6 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
"CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
}
def gen_cmd(comment, a, ba, cmd, delay):
r = "\t/* {0} */\n".format(comment)
r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
if cmd[:12] == "DFII_CONTROL":
r += "\tdfii_control_write({0});\n".format(cmd)
else:
r += "\tcommand_p0({0});\n".format(cmd)
if delay:
r += "\tcdelay({0:d});\n".format(delay)
r += "\n"
return r
r += "static void init_sequence(void)\n{\n"
cl = sdram_phy.phy_settings.cl
if sdram_phy.phy_settings.memtype == "SDR":
@ -218,13 +202,26 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
]
# the value of MR1 needs to be modified during write leveling
r += "#define DDR3_MR1 {}\n\n".format(mr1)
else:
raise NotImplementedError("Unsupported memory type: "+sdram_phy.phy_settings.memtype)
r += "static void init_sequence(void)\n{\n"
for comment, a, ba, cmd, delay in init_sequence:
r += gen_cmd(comment, a, ba, cmd, delay)
r += "\t/* {0} */\n".format(comment)
r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
if cmd[:12] == "DFII_CONTROL":
r += "\tdfii_control_write({0});\n".format(cmd)
else:
r += "\tcommand_p0({0});\n".format(cmd)
if delay:
r += "\tcdelay({0:d});\n".format(delay)
r += "\n"
r += "}\n"
r += "#endif\n"
return r