integration/soc/add_etherbone: Fix typo.

2023-06-09 15:18:23 +02:00 · 2023-06-09 15:18:23 +02:00 · a7ba5771b1
parent c6adf703a3
commit a7ba5771b1
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1732,7 +1732,7 @@ class LiteXSoC(SoC):
                "eth_tx": phy_cd + "_tx",
                "eth_rx": phy_cd + "_rx",
                "sys":    phy_cd + "_rx"})(ethcore)
-        self.add_module(name=f"ethcode_{name}", module=ethcore)
+        self.add_module(name=f"ethcore_{name}", module=ethcore)

        etherbone_cd = "sys"
        if not with_sys_datapath: