remove MiSoC dependency

README

@@ -81,27 +81,20 @@ devel [AT] lists.m-labs.hk.
   python3 setup.py install
   cd ..
 
-3. Obtain MiSoC and install it:
+Note: in case you have issues with Migen, please retry
-  git clone https://github.com/m-labs/misoc --recursive
-  cd misoc
-  python3 setup.py install
-  cd ..
-
-Note: in case you have issues with Migen/MiSoC, please retry
 with our forks at:
-  https://github.com/enjoy-digital/misoc
   https://github.com/enjoy-digital/migen
 until new features are merged.
 
-4. Obtain LiteScope and install it:
+3. Obtain LiteScope and install it:
   git clone https://github.com/enjoy-digital/litescope
 
-5. Build and load test design:
+4. Build and load test design:
   python3 make.py -s [platform] all
-  Supported platforms are the one altready supported by Mibuild:
+  Supported platforms are the ones already supported by Mibuild:
   de0nano, m1, mixxeo, kc705, zedboard...
 
-6. Test design:
+5. Test design:
   go to ./test directory and run:
   python3 test_io.py
   python3 test_la.py

doc/source/docs/getting_started/downloads.rst

@@ -11,31 +11,18 @@ Download and install
   - python3 setup.py install
   - cd ..
 
-3. Obtain LiteScope and install it:
-  - git clone https://github.com/enjoy-digital/litescope
-  - cd litescope
-  - python3 setup.py install
-  - cd ..
-
-4. Obtain MiSoC and install it:
-  - git clone https://github.com/m-labs/misoc --recursive
-  - cd misoc
-  - python3 setup.py install
-  - cd ..
-
 .. note::
-	In case you have issues with Migen/MiSoC, please retry with our forks at:
+	In case you have issues with Migen, please retry with our forks at:
-	https://github.com/enjoy-digital/misoc
 	https://github.com/enjoy-digital/migen
 	until new features are merged.
 
-5. Obtain LiteScope
+3. Obtain LiteScope
   - git clone https://github.com/enjoy-digital/litescope
 
-6. Build and load example design:
+4. Build and load example design:
   - python3 make.py all
 
-7. Test design:
+5. Test design:
   - go to ./test directoryand run:
   - python3 test_io.py
   - python3 test_la.py

make.py

@@ -6,13 +6,22 @@ from mibuild.tools import write_to_file
 from migen.util.misc import autotype
 from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
+from migen.bank.description import CSRStatus
 from mibuild import tools
 from mibuild.xilinx_common import *
 
-from misoclib.gensoc import cpuif
-
 from litescope.common import *
 
+def get_csr_csv(regions):
+	r = ""
+	for name, origin, busword, obj in regions:
+		if not isinstance(obj, Memory):
+			for csr in obj:
+				nr = (csr.size + busword - 1)//busword
+				r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
+				origin += 4*nr
+	return r
+
 def _import(default, name):
 	return importlib.import_module(default + "." + name)
 
@@ -127,7 +136,7 @@ RLE: {}
 		subprocess.call(["rm", "-rf", "build/*"])
 
 	if actions["build-csr-csv"]:
-		csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+		csr_csv = get_csr_csv(soc.cpu_csr_regions)
 		write_to_file(args.csr_csv, csr_csv)
 
 	if actions["build-bitstream"]:

targets/__init__.py

@@ -0,0 +1,26 @@
+import subprocess
+
+from migen.fhdl.std import *
+from migen.bank.description import *
+
+def get_id():
+	output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
+	return int(output[:8], 16)
+
+class Identifier(Module, AutoCSR):
+	def __init__(self, sysid, frequency, revision=None):
+		self._r_sysid = CSRStatus(16)
+		self._r_revision = CSRStatus(32)
+		self._r_frequency = CSRStatus(32)
+
+		###
+
+		if revision is None:
+			revision = get_id()
+
+		self.comb += [
+			self._r_sysid.status.eq(sysid),
+			self._r_revision.status.eq(revision),
+			self._r_frequency.status.eq(frequency),
+		]
+

targets/simple.py

@@ -5,7 +5,7 @@ from migen.bus import wishbone, csr
 from migen.bus import wishbone2csr
 from migen.bank.description import *
 
-from misoclib import identifier
+from targets import *
 
 from litescope.common import *
 from litescope.bridge.uart2wb import LiteScopeUART2WB
@@ -48,7 +48,7 @@ class GenSoC(Module):
 		self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
 
 		# CSR
-		self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
+		self.submodules.identifier = Identifier(0, int(clk_freq))
 
 	def add_cpu_memory_region(self, name, origin, length):
 		self.cpu_memory_regions.append((name, origin, length))