cpu/microwatt: Switch to VHD2VConverter to simplify code.
This commit is contained in:
Florent Kermarrec
parent
3e23ad3cff
commit
a8070051b5
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@ -11,6 +11,9 @@ import os
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from migen import *
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from litex import get_data_mod
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from litex.build.vhd2v_converter import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.gen.common import reverse_bytes
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@ -77,6 +80,7 @@ class Microwatt(CPU):
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# # #
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# CPU Instance.
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self.cpu_params = dict(
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# Clk / Rst.
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i_clk = ClockSignal("sys"),
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@ -126,6 +130,13 @@ class Microwatt(CPU):
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i_core_ext_irq = self.core_ext_irq,
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)
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# VHDL to Verilog Converter.
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self.submodules.cpu_vhd2v_converter = VHD2VConverter(platform,
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top_entity = "microwatt_wrapper",
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build_dir = os.path.abspath(os.path.dirname(__file__)),
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force_convert = ("ghdl" in self.variant),
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)
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# Add VHDL sources.
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self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
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@ -146,8 +157,7 @@ class Microwatt(CPU):
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soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
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soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)
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@staticmethod
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def add_sources(platform, use_ghdl_yosys_plugin=False):
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def add_sources(self, platform, use_ghdl_yosys_plugin=False):
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sources = [
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# Common / Types / Helpers.
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"decode_types.vhdl",
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@ -211,29 +221,11 @@ class Microwatt(CPU):
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sources.append("xilinx-mult.vhdl")
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else:
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sources.append("multiply.vhdl")
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sdir = get_data_mod("cpu", "microwatt").data_location
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cdir = os.path.dirname(__file__)
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# Convert VHDL to Verilog through GHDL/Yosys.
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if use_ghdl_yosys_plugin:
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from litex.build import tools
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import subprocess
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ys = []
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ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
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for source in sources:
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ys.append(os.path.join(sdir, source) + " \\")
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ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\")
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ys.append("-e microwatt_wrapper")
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ys.append("chformal -assert -remove")
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ys.append("write_verilog {}".format(os.path.join(cdir, "microwatt.v")))
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tools.write_to_file(os.path.join(cdir, "microwatt.ys"), "\n".join(ys))
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if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]):
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raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install")
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platform.add_source(os.path.join(cdir, "microwatt.v"))
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# Direct use of VHDL sources.
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else:
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platform.add_sources(sdir, *sources)
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platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
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self.cpu_vhd2v_converter.add_sources(sdir, *sources)
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self.cpu_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
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def do_finalize(self):
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self.specials += Instance("microwatt_wrapper", **self.cpu_params)
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@ -247,10 +239,11 @@ class XICSSlave(Module, AutoCSR):
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self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12)
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self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12)
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# XICS signals.
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# XICS Signals.
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self.ics_icp_xfer_src = Signal(4)
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self.ics_icp_xfer_pri = Signal(8)
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# XICS Instance.
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self.icp_params = dict(
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# Clk / Rst.
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i_clk = ClockSignal("sys"),
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@ -295,6 +288,18 @@ class XICSSlave(Module, AutoCSR):
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o_icp_out_pri = self.ics_icp_xfer_pri,
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)
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# VHDL to Verilog Converter.
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self.submodules.icp_vhd2v_converter = VHD2VConverter(platform,
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top_entity = "xics_icp_wrapper",
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build_dir = os.path.abspath(os.path.dirname(__file__)),
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force_convert = ("ghdl" in self.variant),
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)
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self.submodules.ics_vhd2v_converter = VHD2VConverter(platform,
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top_entity = "xics_ics_wrapper",
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build_dir = os.path.abspath(os.path.dirname(__file__)),
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force_convert = ("ghdl" in self.variant),
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)
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# Add VHDL sources.
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self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
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@ -313,40 +318,10 @@ class XICSSlave(Module, AutoCSR):
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]
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sdir = get_data_mod("cpu", "microwatt").data_location
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cdir = os.path.dirname(__file__)
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if use_ghdl_yosys_plugin:
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from litex.build import tools
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import subprocess
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# ICP
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ys = []
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ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
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for source in sources:
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ys.append(os.path.join(sdir, source) + " \\")
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ys.append(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl") + " \\")
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ys.append("-e xics_icp_wrapper")
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ys.append("chformal -assert -remove")
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ys.append("write_verilog {}".format(os.path.join(cdir, "xics_icp.v")))
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tools.write_to_file(os.path.join(cdir, "xics_icp.ys"), "\n".join(ys))
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if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "xics_icp.ys")]):
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raise OSError("Unable to convert Microwatt XICS ICP controller to verilog, please check your GHDL-Yosys-plugin install")
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platform.add_source(os.path.join(cdir, "xics_icp.v"))
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# ICS
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ys = []
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ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
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for source in sources:
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ys.append(os.path.join(sdir, source) + " \\")
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ys.append(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl") + " \\")
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ys.append("-e xics_ics_wrapper")
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ys.append("chformal -assert -remove")
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ys.append("write_verilog {}".format(os.path.join(cdir, "xics_ics.v")))
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tools.write_to_file(os.path.join(cdir, "xics_ics.ys"), "\n".join(ys))
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if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "xics_ics.ys")]):
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raise OSError("Unable to convert Microwatt XICS ICP controller to verilog, please check your GHDL-Yosys-plugin install")
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platform.add_source(os.path.join(cdir, "xics_ics.v"))
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else:
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platform.add_sources(sdir, *sources)
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platform.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
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self.ics_vhd2v_converter.add_sources(sdir, *sources)
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self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
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self.icp_vhd2v_converter.add_sources(sdir, *sources)
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self.icp_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
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def do_finalize(self):
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self.specials += Instance("xics_icp_wrapper", **self.icp_params)
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