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cpu/microwatt: Switch to VHD2VConverter to simplify code.

This commit is contained in:
Florent Kermarrec 2022-10-13 09:23:20 +02:00
parent 3e23ad3cff
commit a8070051b5
1 changed files with 33 additions and 58 deletions
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91
litex/soc/cores/cpu/microwatt/core.py
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@ -11,6 +11,9 @@ import os
from migen import * from migen import *
from litex import get_data_mod from litex import get_data_mod
from litex.build.vhd2v_converter import *
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.gen.common import reverse_bytes from litex.gen.common import reverse_bytes
@ -77,6 +80,7 @@ class Microwatt(CPU):
# # # # # #
# CPU Instance.
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal("sys"), i_clk = ClockSignal("sys"),
@ -126,6 +130,13 @@ class Microwatt(CPU):
i_core_ext_irq = self.core_ext_irq, i_core_ext_irq = self.core_ext_irq,
) )
# VHDL to Verilog Converter.
self.submodules.cpu_vhd2v_converter = VHD2VConverter(platform,
top_entity = "microwatt_wrapper",
build_dir = os.path.abspath(os.path.dirname(__file__)),
force_convert = ("ghdl" in self.variant),
)
# Add VHDL sources. # Add VHDL sources.
self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
@ -146,8 +157,7 @@ class Microwatt(CPU):
soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region) soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region) soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)
@staticmethod def add_sources(self, platform, use_ghdl_yosys_plugin=False):
def add_sources(platform, use_ghdl_yosys_plugin=False):
sources = [ sources = [
# Common / Types / Helpers. # Common / Types / Helpers.
"decode_types.vhdl", "decode_types.vhdl",
@ -211,29 +221,11 @@ class Microwatt(CPU):
sources.append("xilinx-mult.vhdl") sources.append("xilinx-mult.vhdl")
else: else:
sources.append("multiply.vhdl") sources.append("multiply.vhdl")
sdir = get_data_mod("cpu", "microwatt").data_location sdir = get_data_mod("cpu", "microwatt").data_location
cdir = os.path.dirname(__file__) cdir = os.path.dirname(__file__)
# Convert VHDL to Verilog through GHDL/Yosys. self.cpu_vhd2v_converter.add_sources(sdir, *sources)
if use_ghdl_yosys_plugin: self.cpu_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
from litex.build import tools
import subprocess
ys = []
ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
for source in sources:
ys.append(os.path.join(sdir, source) + " \\")
ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\")
ys.append("-e microwatt_wrapper")
ys.append("chformal -assert -remove")
ys.append("write_verilog {}".format(os.path.join(cdir, "microwatt.v")))
tools.write_to_file(os.path.join(cdir, "microwatt.ys"), "\n".join(ys))
if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]):
raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install")
platform.add_source(os.path.join(cdir, "microwatt.v"))
# Direct use of VHDL sources.
else:
platform.add_sources(sdir, *sources)
platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
def do_finalize(self): def do_finalize(self):
self.specials += Instance("microwatt_wrapper", **self.cpu_params) self.specials += Instance("microwatt_wrapper", **self.cpu_params)
@ -247,10 +239,11 @@ class XICSSlave(Module, AutoCSR):
self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12) self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12)
self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12) self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12)
# XICS signals. # XICS Signals.
self.ics_icp_xfer_src = Signal(4) self.ics_icp_xfer_src = Signal(4)
self.ics_icp_xfer_pri = Signal(8) self.ics_icp_xfer_pri = Signal(8)
# XICS Instance.
self.icp_params = dict( self.icp_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal("sys"), i_clk = ClockSignal("sys"),
@ -295,6 +288,18 @@ class XICSSlave(Module, AutoCSR):
o_icp_out_pri = self.ics_icp_xfer_pri, o_icp_out_pri = self.ics_icp_xfer_pri,
) )
# VHDL to Verilog Converter.
self.submodules.icp_vhd2v_converter = VHD2VConverter(platform,
top_entity = "xics_icp_wrapper",
build_dir = os.path.abspath(os.path.dirname(__file__)),
force_convert = ("ghdl" in self.variant),
)
self.submodules.ics_vhd2v_converter = VHD2VConverter(platform,
top_entity = "xics_ics_wrapper",
build_dir = os.path.abspath(os.path.dirname(__file__)),
force_convert = ("ghdl" in self.variant),
)
# Add VHDL sources. # Add VHDL sources.
self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
@ -313,40 +318,10 @@ class XICSSlave(Module, AutoCSR):
] ]
sdir = get_data_mod("cpu", "microwatt").data_location sdir = get_data_mod("cpu", "microwatt").data_location
cdir = os.path.dirname(__file__) cdir = os.path.dirname(__file__)
if use_ghdl_yosys_plugin: self.ics_vhd2v_converter.add_sources(sdir, *sources)
from litex.build import tools self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
import subprocess self.icp_vhd2v_converter.add_sources(sdir, *sources)
self.icp_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
# ICP
ys = []
ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
for source in sources:
ys.append(os.path.join(sdir, source) + " \\")
ys.append(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl") + " \\")
ys.append("-e xics_icp_wrapper")
ys.append("chformal -assert -remove")
ys.append("write_verilog {}".format(os.path.join(cdir, "xics_icp.v")))
tools.write_to_file(os.path.join(cdir, "xics_icp.ys"), "\n".join(ys))
if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "xics_icp.ys")]):
raise OSError("Unable to convert Microwatt XICS ICP controller to verilog, please check your GHDL-Yosys-plugin install")
platform.add_source(os.path.join(cdir, "xics_icp.v"))
# ICS
ys = []
ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
for source in sources:
ys.append(os.path.join(sdir, source) + " \\")
ys.append(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl") + " \\")
ys.append("-e xics_ics_wrapper")
ys.append("chformal -assert -remove")
ys.append("write_verilog {}".format(os.path.join(cdir, "xics_ics.v")))
tools.write_to_file(os.path.join(cdir, "xics_ics.ys"), "\n".join(ys))
if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "xics_ics.ys")]):
raise OSError("Unable to convert Microwatt XICS ICP controller to verilog, please check your GHDL-Yosys-plugin install")
platform.add_source(os.path.join(cdir, "xics_ics.v"))
else:
platform.add_sources(sdir, *sources)
platform.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
def do_finalize(self): def do_finalize(self):
self.specials += Instance("xics_icp_wrapper", **self.icp_params) self.specials += Instance("xics_icp_wrapper", **self.icp_params)