Revert "sim/core: fix Cat bitshift"

This reverts commit 6d6f91a02b.
2015-10-19 16:08:42 +08:00 · 2015-10-19 16:08:42 +08:00 · a824046bbc
parent 6d6f91a02b
commit a824046bbc
1 changed files with 1 additions and 2 deletions
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@ -156,11 +156,10 @@ class Evaluator:
                value -= 2**node.nbits
            self.modifications[node] = value
        elif isinstance(node, Cat):
-            nbits = 0
            for element in node.l:
-                value >>= nbits
                nbits = len(element)
                self.assign(element, value & (2**nbits-1))
+                value >>= nbits
        elif isinstance(node, _Slice):
            full_value = self.eval(node.value, True)
            # clear bits assigned to by the slice