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Revert "sim/core: fix Cat bitshift" 

This reverts commit 6d6f91a02b.
This commit is contained in:
Sebastien Bourdeauducq 2015-10-19 16:08:42 +08:00
parent 6d6f91a02b
commit a824046bbc
1 changed files with 1 additions and 2 deletions
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3
migen/sim/core.py
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@ -156,11 +156,10 @@ class Evaluator:
value -= 2**node.nbits value -= 2**node.nbits
self.modifications[node] = value self.modifications[node] = value
elif isinstance(node, Cat): elif isinstance(node, Cat):
nbits = 0
for element in node.l: for element in node.l:
value >>= nbits
nbits = len(element) nbits = len(element)
self.assign(element, value & (2**nbits-1)) self.assign(element, value & (2**nbits-1))
value >>= nbits
elif isinstance(node, _Slice): elif isinstance(node, _Slice):
full_value = self.eval(node.value, True) full_value = self.eval(node.value, True)
# clear bits assigned to by the slice # clear bits assigned to by the slice