Xilinx: Initial openxc7 toolchain support
This commit is contained in:
Hans Baier
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7e6418900a
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import subprocess
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import sys
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import math
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from typing import NamedTuple, Union, List
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import re
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from shutil import which
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from migen.fhdl.structure import _Fragment, wrap, Constant
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from migen.fhdl.specials import Instance
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from litex.build.yosys_nextpnr_toolchain import YosysNextPNRToolchain
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from litex.build.generic_platform import *
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from litex.build.xilinx.vivado import _xdc_separator, _format_xdc, _build_xdc
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from litex.build import tools
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from litex.build.xilinx import common
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def _unwrap(value):
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return value.value if isinstance(value, Constant) else value
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# XilinxOpenXC7Toolchain ----------------------------------------------------------------------------
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class XilinxOpenXC7Toolchain(YosysNextPNRToolchain):
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attr_translate = {}
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synth_fmt = "json"
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constr_fmt = "xdc"
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pnr_fmt = "fasm"
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packer_cmd = "xc7frames2bit"
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def __init__(self):
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super().__init__()
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self.dbpart = None
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self.family = "xilinx"
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self._xc7family = None
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self._clock_constraints = ""
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self.additional_xdc_commands = []
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self._pre_packer_cmd = ["fasm2frames"]
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self._synth_opts = "-flatten -abc9 -arch xc7 "
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xc7_family_map = {
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"a": "artix7",
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"k": "kintex7",
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"s": "spartan7",
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"z": "zynq7"
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}
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def _check_properties(self):
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pattern = re.compile("xc7([aksz])([0-9]+)(.*)-([0-9])")
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g = pattern.search(self.platform.device)
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if not self.dbpart:
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self.dbpart = f"xc7{g.group(1)}{g.group(2)}{g.group(3)}"
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if not self._xc7family:
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fam = g.group(1)
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self._xc7family = self.xc7_family_map[fam]
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def build_timing_constraints(self, vns):
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xdc = []
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xdc.append(_xdc_separator("Clock constraints"))
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for clk, [period, name] in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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clk_sig = self._vns.get_name(clk)
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if name is None:
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name = clk_sig
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xdc.append(
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"create_clock -name {name} -period " + str(period) +
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" [get_ports {clk}]".format(name=name, clk=clk_sig))
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# generate sdc
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xdc += self.additional_xdc_commands
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self._clock_constraints = "\n".join(xdc)
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def build_io_constraints(self):
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tools.write_to_file(self._build_name + ".xdc", _build_xdc(self.named_sc, self.named_pc) + self._clock_constraints)
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return (self._build_name + ".xdc", "XDC")
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def _fix_instance(self, instance):
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pass
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def finalize(self):
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# toolchain-specific fixes
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for instance in self.fragment.specials:
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if isinstance(instance, Instance):
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self._fix_instance(instance)
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chipdb_dir = os.environ.get('CHIPDB')
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if chipdb_dir is None or chipdb_dir == "":
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print("Error: please specify the directory, where you store your nextpnr-xilinx chipdb files in the environment variable CHIPDB (may be empty)")
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exit(1)
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# pnr options
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self._pnr_opts += "--chipdb {chipdb_dir}/{dbpart}.bin --write {top}_routed.json".format(
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top = self._build_name,
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chipdb_dir = chipdb_dir,
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dbpart = self.dbpart,
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)
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prjxray_db_dir = os.environ.get('PRJXRAY_DB_DIR')
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if prjxray_db_dir is None or prjxray_db_dir == "":
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prjxray_db_dir = '/snap/openxc7/current/opt/nextpnr-xilinx/external/prjxray-db/'
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if not os.path.isdir(prjxray_db_dir):
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print(f"{prjxray_db_dir} does not exist on your system. \n" + \
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"Do you have the openXC7 toolchain installed? \n" + \
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"You can get it here: https://github.com/openXC7/toolchain-installer")
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exit(1)
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# pre packer options
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self._pre_packer_opts["fasm2frames"] = "--part {part} --db-root {db_root} {top}.fasm > {top}.frames".format(
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part = self.platform.device,
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db_root = os.path.join(prjxray_db_dir, self._xc7family),
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top = self._build_name
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)
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# packer options
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self._packer_opts += "--part_file {db_dir}/{part}/part.yaml --part_name {part} --frm_file {top}.frames --output_file {top}.bit".format(
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db_dir = os.path.join(prjxray_db_dir, self._xc7family),
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part = self.platform.device,
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top = self._build_name
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)
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return YosysNextPNRToolchain.finalize(self)
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def build(self, platform, fragment,
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enable_xpm = False,
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**kwargs):
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self.platform = platform
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self._check_properties()
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return YosysNextPNRToolchain.build(self, platform, fragment, **kwargs)
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def add_false_path_constraint(self, platform, from_, to):
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# FIXME: false path constraints are currently not supported by the openXC7 toolchain
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return
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@ -21,7 +21,7 @@ class XilinxPlatform(GenericPlatform):
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_supported_toolchains = {
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"spartan6" : ["ise"],
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"7series" : ["vivado", "f4pga", "yosys+nextpnr"],
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"7series" : ["vivado", "f4pga", "yosys+nextpnr", "openxc7"],
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"ultrascale" : ["vivado"],
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"ultrascale+" : ["vivado"],
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}
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@ -42,6 +42,9 @@ class XilinxPlatform(GenericPlatform):
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elif toolchain == "yosys+nextpnr":
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from litex.build.xilinx import yosys_nextpnr
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self.toolchain = yosys_nextpnr.XilinxYosysNextpnrToolchain()
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elif toolchain == "openxc7":
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from litex.build.xilinx import openxc7
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self.toolchain = openxc7.XilinxOpenXC7Toolchain()
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else:
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raise ValueError(f"Unknown toolchain {toolchain}")
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@ -45,7 +45,7 @@ class XilinxYosysNextpnrToolchain(YosysNextPNRToolchain):
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self.bitstream_device = None
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self._partname = None
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self._pre_packer_cmd = ["fasm2frames.py"]
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self._synth_opts = "-flatten -abc9 -nobram -arch xc7 "
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self._synth_opts = "-flatten -abc9 -arch xc7 "
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def _check_properties(self):
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if not self.f4pga_device:
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@ -64,12 +64,14 @@ class XilinxYosysNextpnrToolchain(YosysNextPNRToolchain):
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# bitstream_device points to a directory in prjxray database
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# available bitstream_devices: artix7, kintex7, zynq7
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self.bitstream_device = {
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"xc7a": "artix7", # xc7a35t, xc7a50t, xc7a100t, xc7a200t
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"xc7z": "zynq7", # xc7z010, xc7z020
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"xc7s": "spartan7",
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"xc7a": "artix7",
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"xc7k": "kintex7",
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"xc7z": "zynq7",
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}[self.platform.device[:4]]
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except KeyError:
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raise ValueError(f"Unsupported device: {self.platform.device}")
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# FIXME: prjxray-db doesn't have xc7a35ticsg324-1L - use closest replacement
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self._partname = {
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"xc7a35ticsg324-1L" : "xc7a35tcsg324-1",
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"xc7a100tcsg324-1" : "xc7a100tcsg324-1",
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@ -132,12 +134,5 @@ class XilinxYosysNextpnrToolchain(YosysNextPNRToolchain):
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return YosysNextPNRToolchain.build(self, platform, fragment, **kwargs)
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def add_false_path_constraint(self, platform, from_, to):
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# FIXME: false path constraints are currently not supported by the F4PGA toolchain
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# FIXME: false path constraints are currently not supported by nextpnr-xilinx
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return
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def f4pga_build_args(parser):
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pass
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def f4pga_build_argdict(args):
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return dict()
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