Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/versa_ecp5: fix compilation with diamond

This commit is contained in:
Florent Kermarrec 2019-12-06 16:15:08 +01:00
parent 30a18808ad
commit a8635c48a4
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litex/boards/targets/versa_ecp5.py
View File

@ -139,7 +139,10 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args)) builder_kargs = {}
if args.toolchain == "trellis":
builder_kargs == trellis_argdict(args)
builder.build(**builder_kargs)
if __name__ == "__main__": if __name__ == "__main__":
main() main()