mila: symplify usage

This commit is contained in:
Florent Kermarrec 2013-09-22 13:28:12 +02:00
parent 27f26dac03
commit a880862628
2 changed files with 16 additions and 15 deletions

View File

@ -20,8 +20,7 @@ from migen.bank import csrgen
from miscope.std.misc import *
from miscope.trigger import Term, RangeDetector, EdgeDetector, Sum, Trigger
from miscope.storage import Recorder
from miscope.trigger import Term
from miscope.miio import MiIo
from miscope.mila import MiLa
@ -37,9 +36,8 @@ from timings import *
clk_freq = 50*MHz
# Mila Param
trig_w = 16
dat_w = 16
rec_size = 4096
mila_width = 16
mila_depth = 4096
#==============================================================================
# M I S C O P E E X A M P L E
@ -51,17 +49,13 @@ class SoC(Module):
"mila": 2,
}
def __init__(self, platform):
# MiIo
self.submodules.miio = MiIo(8)
# MiLa
term = Term(trig_w)
trigger = Trigger(trig_w, [term])
recorder = Recorder(dat_w, rec_size)
self.submodules.mila = MiLa(trigger, recorder)
term = Term(mila_width)
self.submodules.mila = MiLa(mila_width, mila_depth, [term])
# Uart2Csr
self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)

View File

@ -5,13 +5,20 @@ from migen.bus import csr
from migen.bank import description, csrgen
from migen.bank.description import *
from miscope.trigger import Trigger
from miscope.storage import Recorder
class MiLa(Module, AutoCSR):
def __init__(self, trigger, recorder):
self.trigger = trigger
self.recorder = recorder
def __init__(self, width, depth, ports):
self.width = width
trigger = Trigger(width, ports)
recorder = Recorder(width, depth)
self.submodules.trigger = trigger
self.submodules.recorder = recorder
self.sink = trigger.sink
self.submodules += trigger, recorder
self.comb +=[
recorder.sink.stb.eq(trigger.source.stb),