software/liblitedram: allow cmd_delay adjustment even when enforced by the phy.
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@ -107,6 +107,7 @@ void sdram_mode_register_write(char reg, int value) {
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#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
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int _sdram_write_leveling_cmd_scan = 1;
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int _sdram_write_leveling_cmd_delay = 0;
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int _sdram_write_leveling_dat_delays[16];
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static void sdram_write_leveling_on(void)
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@ -147,6 +148,7 @@ void sdram_write_leveling_rst_cmd_delay(int show) {
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void sdram_write_leveling_force_cmd_delay(int taps, int show) {
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_sdram_write_leveling_cmd_scan = 0;
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_sdram_write_leveling_cmd_delay = taps;
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if (show)
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printf("Forcing Cmd delay to %d taps\n", taps);
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ddrphy_cdly_rst_write(1);
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@ -371,7 +373,8 @@ int sdram_write_leveling(void)
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int cdly_range_end;
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int cdly_range_step;
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#ifndef SDRAM_PHY_CMD_DELAY
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if (_sdram_write_leveling_cmd_scan) {
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printf(" Cmd/Clk scan:\n");
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/* Center write leveling by varying cdly. Searching through all possible
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@ -403,9 +406,9 @@ int sdram_write_leveling(void)
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cdly_range_step /= 4;
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}
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printf("| best: %d\n", best_cdly);
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#else
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best_cdly = SDRAM_PHY_CMD_DELAY;
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#endif
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} else {
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best_cdly = _sdram_write_leveling_cmd_delay;
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}
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printf(" Setting Cmd/Clk delay to %d taps.\n", best_cdly);
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/* set working or forced delay */
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if (best_cdly >= 0) {
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@ -755,13 +758,7 @@ int sdram_leveling(void)
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#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
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printf("Write leveling:\n");
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if (_sdram_write_leveling_cmd_scan) {
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sdram_write_leveling();
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} else {
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/* use only the current cdly */
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int delays[SDRAM_PHY_MODULES];
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sdram_write_leveling_scan(delays, 128, 1);
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}
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#endif
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#ifdef SDRAM_PHY_READ_LEVELING_CAPABLE
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@ -785,6 +782,10 @@ int sdram_init(void)
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int i;
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sdram_write_leveling_rst_cmd_delay(0);
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for (i=0; i<16; i++) sdram_write_leveling_rst_dat_delay(i, 0);
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#endif
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#ifdef SDRAM_PHY_CMD_DELAY
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_sdram_write_leveling_cmd_scan = 0;
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_sdram_write_leveling_cmd_delay = SDRAM_PHY_CMD_DELAY;
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#endif
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printf("Initializing SDRAM @0x%08x...\n", MAIN_RAM_BASE);
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sdram_software_control_on();
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