Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)

This commit is contained in:
Florent Kermarrec 2015-03-28 01:17:50 +01:00
parent 7fe748e1b0
commit a95b3f8f13
2 changed files with 56 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
misoclib/mem/sdram/core/lasmicon/__init__.py
View File

@ -11,7 +11,8 @@ class LASMIconSettings:
read_time=32, write_time=16,
with_l2=True, l2_size=8192,
with_bandwidth=False,
with_memtest=False):
with_memtest=False,
with_refresh=True):
self.req_queue_size = req_queue_size
self.read_time = read_time
self.write_time = write_time
@ -22,6 +23,7 @@ class LASMIconSettings:
else:
self.with_bandwidth = with_bandwidth
self.with_memtest = with_memtest
self.with_refresh = with_refresh
class LASMIcon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
@ -47,7 +49,7 @@ class LASMIcon(Module):
###
self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC, enabled=controller_settings.with_refresh)
self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
getattr(self.lasmic, "bank"+str(i)))
for i in range(2**geom_settings.bankbits)]

103
misoclib/mem/sdram/core/lasmicon/refresher.py
View File

@ -5,64 +5,65 @@ from migen.genlib.fsm import FSM
from misoclib.mem.sdram.core.lasmicon.multiplexer import *
class Refresher(Module):
def __init__(self, a, ba, tRP, tREFI, tRFC):
def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
self.req = Signal()
self.ack = Signal() # 1st command 1 cycle after assertion of ack
self.cmd = CommandRequest(a, ba)
###
# Refresh sequence generator:
# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
seq_start = Signal()
seq_done = Signal()
self.sync += [
self.cmd.a.eq(2**10),
self.cmd.ba.eq(0),
self.cmd.cas_n.eq(1),
self.cmd.ras_n.eq(1),
self.cmd.we_n.eq(1),
seq_done.eq(0)
]
self.sync += timeline(seq_start, [
(1, [
self.cmd.ras_n.eq(0),
self.cmd.we_n.eq(0)
]),
(1+tRP, [
self.cmd.cas_n.eq(0),
self.cmd.ras_n.eq(0)
]),
(1+tRP+tRFC, [
seq_done.eq(1)
if enabled:
# Refresh sequence generator:
# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
seq_start = Signal()
seq_done = Signal()
self.sync += [
self.cmd.a.eq(2**10),
self.cmd.ba.eq(0),
self.cmd.cas_n.eq(1),
self.cmd.ras_n.eq(1),
self.cmd.we_n.eq(1),
seq_done.eq(0)
]
self.sync += timeline(seq_start, [
(1, [
self.cmd.ras_n.eq(0),
self.cmd.we_n.eq(0)
]),
(1+tRP, [
self.cmd.cas_n.eq(0),
self.cmd.ras_n.eq(0)
]),
(1+tRP+tRFC, [
seq_done.eq(1)
])
])
])
# Periodic refresh counter
counter = Signal(max=tREFI)
start = Signal()
self.sync += [
start.eq(0),
If(counter == 0,
start.eq(1),
counter.eq(tREFI - 1)
).Else(
counter.eq(counter - 1)
)
]
# Periodic refresh counter
counter = Signal(max=tREFI)
start = Signal()
self.sync += [
start.eq(0),
If(counter == 0,
start.eq(1),
counter.eq(tREFI - 1)
).Else(
counter.eq(counter - 1)
)
]
# Control FSM
fsm = FSM()
self.submodules += fsm
fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
fsm.act("WAIT_GRANT",
self.req.eq(1),
If(self.ack,
seq_start.eq(1),
NextState("WAIT_SEQ")
# Control FSM
fsm = FSM()
self.submodules += fsm
fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
fsm.act("WAIT_GRANT",
self.req.eq(1),
If(self.ack,
seq_start.eq(1),
NextState("WAIT_SEQ")
)
)
fsm.act("WAIT_SEQ",
self.req.eq(1),
If(seq_done, NextState("IDLE"))
)
)
fsm.act("WAIT_SEQ",
self.req.eq(1),
If(seq_done, NextState("IDLE"))
)