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build/efinix: Minor initial cleanups.

This commit is contained in:
Florent Kermarrec 2021-10-13 09:42:39 +02:00
parent eafa0fe83e
commit a99b4cac48
8 changed files with 146 additions and 103 deletions
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4
litex/build/efinix/common.py
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@ -10,7 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import * from litex.build.io import *
# Efinix AsyncResetSynchronizer --------------------------------------------------------------------- # Efinix AsyncResetSynchronizer --------------------------------------------------------------------
class EfinixAsyncResetSynchronizerImpl(Module): class EfinixAsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset): def __init__(self, cd, async_reset):
@ -36,7 +36,7 @@ class EfinixAsyncResetSynchronizer:
def lower(dr): def lower(dr):
return EfinixAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) return EfinixAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
# Gowin Special Overrides -------------------------------------------------------------------------- # Efinix Special Overrides -------------------------------------------------------------------------
efinix_special_overrides = { efinix_special_overrides = {
AsyncResetSynchronizer: EfinixAsyncResetSynchronizer AsyncResetSynchronizer: EfinixAsyncResetSynchronizer

15
litex/build/efinix/dbparser.py
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@ -1,13 +1,24 @@
#
# This file is part of LiteX.
#
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
# SPDX-License-Identifier: BSD-2-Clause
import os import os
import csv import csv
import re import re
import xml.etree.ElementTree as et import xml.etree.ElementTree as et
namespaces = { 'efxpt' : 'http://www.efinixinc.com/peri_device_db', # NameSpaces ---------------------------------------------------------------------------------------
'xi' : 'http://www.w3.org/2001/XInclude'
namespaces = {
'efxpt' : "http://www.efinixinc.com/peri_device_db",
'xi' : "http://www.w3.org/2001/XInclude"
} }
# Efinix Database Parser ---------------------------------------------------------------------------
class EfinixDbParser(): class EfinixDbParser():
def __init__(self, efinity_path, device): def __init__(self, efinity_path, device):
self.efinity_db_path = efinity_path + '/pt/db/' self.efinity_db_path = efinity_path + '/pt/db/'

19
litex/build/efinix/ddr.py
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@ -1,3 +1,11 @@
#
# This file is part of LiteX.
#
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
# SPDX-License-Identifier: BSD-2-Clause
# FIXME: Cleanup/Move.
import os import os
from migen import * from migen import *
@ -9,6 +17,8 @@ from litex.soc.interconnect import axi
from litex.build import tools from litex.build import tools
# Efinix DDR ---------------------------------------------------------------------------------------
class EfinixDDR(Module): class EfinixDDR(Module):
def __init__(self, platform, config, cd): def __init__(self, platform, config, cd):
self.blocks = [] self.blocks = []
@ -16,8 +26,8 @@ class EfinixDDR(Module):
self.config = config self.config = config
self.nb_ports = 1 self.nb_ports = 1
if config['ports'] != None: if config["ports"] != None:
self.nb_ports = self.config['ports'] self.nb_ports = self.config["ports"]
# TODO: set clock_domain ? # TODO: set clock_domain ?
self.port0 = port0 = axi.AXIInterface(data_width=256, address_width=32, id_width=8) self.port0 = port0 = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
@ -25,7 +35,7 @@ class EfinixDDR(Module):
if self.nb_ports == 2: if self.nb_ports == 2:
self.port1 = port1 = axi.AXIInterface(data_width=256, address_width=32, id_width=8) self.port1 = port1 = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
for i in range (0, self.nb_ports): for i in range(self.nb_ports):
ios = [('axi', i, ios = [('axi', i,
Subsignal('wdata', Pins(256)), Subsignal('wdata', Pins(256)),
Subsignal('wready', Pins(1)), Subsignal('wready', Pins(1)),
@ -60,7 +70,8 @@ class EfinixDDR(Module):
port = port1 port = port1
is_read = port.ar.valid is_read = port.ar.valid
self.comb += [io.aaddr.eq(Mux(is_read, port.ar.addr, port.aw.addr)), self.comb += [
io.aaddr.eq(Mux(is_read, port.ar.addr, port.aw.addr)),
io.aid.eq(Mux(is_read, port.ar.id, port.aw.id)), io.aid.eq(Mux(is_read, port.ar.id, port.aw.id)),
io.alen.eq(Mux(is_read, port.ar.len, port.aw.len)), io.alen.eq(Mux(is_read, port.ar.len, port.aw.len)),
io.asize.eq(Mux(is_read, port.ar.size[0:4], port.aw.size[0:4])), #TODO: check io.asize.eq(Mux(is_read, port.ar.size[0:4], port.aw.size[0:4])), #TODO: check

2
litex/build/efinix/efinity.py
View File

@ -29,6 +29,8 @@ from litex.build import tools
from litex.build.efinix import InterfaceWriter from litex.build.efinix import InterfaceWriter
# FIXME: Avoid duplication with verilog.py.
_reserved_keywords = { _reserved_keywords = {
"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1", "always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default", "case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",

25
litex/build/efinix/ifacewriter.py
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@ -1,3 +1,9 @@
#
# This file is part of LiteX.
#
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
# SPDX-License-Identifier: BSD-2-Clause
import os import os
import csv import csv
import re import re
@ -8,10 +14,13 @@ import xml.etree.ElementTree as et
from litex.build import tools from litex.build import tools
namespaces = { 'efxpt' : 'http://www.efinixinc.com/peri_design_db', namespaces = {
'xi' : 'http://www.w3.org/2001/XInclude' "efxpt" : "http://www.efinixinc.com/peri_design_db",
"xi" : "http://www.w3.org/2001/XInclude"
} }
# Interface Writer --------------------------------------------------------------------------------
class InterfaceWriter(): class InterfaceWriter():
def __init__(self, efinity_path): def __init__(self, efinity_path):
self.efinity_path = efinity_path self.efinity_path = efinity_path
@ -66,9 +75,11 @@ class InterfaceWriter():
lvds = et.SubElement(lvds_info, 'efxpt:lvds', lvds = et.SubElement(lvds_info, 'efxpt:lvds',
name = params['name'], name = params['name'],
lvds_def = pad, lvds_def = pad,
ops_type = dir) ops_type = dir
)
et.SubElement(lvds, 'efxpt:ltx_info', pll_instance = '', et.SubElement(lvds, 'efxpt:ltx_info',
pll_instance = '',
fast_clock_name = '{}'.format(params['fast_clk']), fast_clock_name = '{}'.format(params['fast_clk']),
slow_clock_name = '{}'.format(params['slow_clk']), slow_clock_name = '{}'.format(params['slow_clk']),
reset_name = '', reset_name = '',
@ -78,7 +89,8 @@ class InterfaceWriter():
mode = '{}'.format(mode), mode = '{}'.format(mode),
serialization = '{}'.format(params['serialisation']), serialization = '{}'.format(params['serialisation']),
reduced_swing = 'false', reduced_swing = 'false',
load = '3') load = '3'
)
def add_ddr_xml(self, root, params): def add_ddr_xml(self, root, params):
@ -95,7 +107,8 @@ class InterfaceWriter():
cs_speedbin = '800', cs_speedbin = '800',
target0_enable = 'true', target0_enable = 'true',
target1_enable = 'false', target1_enable = 'false',
ctrl_type = 'none') ctrl_type = 'none'
)
axi_suffix = '' # '_1' for second port axi_suffix = '' # '_1' for second port
type_suffix = '_0' # '_1' for second port type_suffix = '_0' # '_1' for second port

2
litex/build/efinix/programmer.py
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@ -10,6 +10,8 @@ import subprocess
from litex.build.generic_programmer import GenericProgrammer from litex.build.generic_programmer import GenericProgrammer
# EfinixProgrammer ---------------------------------------------------------------------------------
class EfinixProgrammer(GenericProgrammer): class EfinixProgrammer(GenericProgrammer):
def __init__(self, cable_name=""): def __init__(self, cable_name=""):

4
litex/build/efinix/rgmii.py
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@ -5,7 +5,9 @@
# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
# RGMII PHY for 7-Series Xilinx FPGA # RGMII PHY for Efinix FPGAs
# FIXME: Cleanup/Move.
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer

2
litex/build/efinix/video.py
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@ -4,6 +4,8 @@
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
# FIXME: Cleanup/Move, integrate in soc.cores.video.
import os import os
import math import math