soc/add_pcie: Add msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
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@ -29,6 +29,7 @@
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- software/liblitespi : Added read_id support.
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- software/liblitespi : Added read_id support.
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- litex_boards : Added QMtech XC7K325T, VCU128, SITLINV_STVL7325_V2, Enclustra XU8/PE3 support.
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- litex_boards : Added QMtech XC7K325T, VCU128, SITLINV_STVL7325_V2, Enclustra XU8/PE3 support.
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- liteeth : Added Ultrascale+ GTY/GTH SGMII/1000BaseX PHYs.
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- liteeth : Added Ultrascale+ GTY/GTH SGMII/1000BaseX PHYs.
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- soc/add_pcie : Added msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
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[> Changed
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[> Changed
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----------
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----------
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@ -1976,12 +1976,12 @@ class LiteXSoC(SoC):
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with_dma_synchronizer = False,
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with_dma_synchronizer = False,
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with_dma_monitor = False,
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with_dma_monitor = False,
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with_dma_status = False,
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with_dma_status = False,
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with_msi = True,
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with_msi = True, msi_type="msi",
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):
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):
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# Imports
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# Imports
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from litepcie.phy.uspciephy import USPCIEPHY
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from litepcie.phy.uspciephy import USPCIEPHY
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI, LitePCIeMSIMultiVector, LitePCIeMSIX
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneMaster
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from litepcie.frontend.wishbone import LitePCIeWishboneMaster
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@ -2005,11 +2005,18 @@ class LiteXSoC(SoC):
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# MSI.
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# MSI.
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if with_msi:
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if with_msi:
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assert msi_type in ["msi", "msi-multi-vector", "msi-x"]
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self.check_if_exists(f"{name}_msi")
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self.check_if_exists(f"{name}_msi")
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if msi_type == "msi":
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msi = LitePCIeMSI()
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msi = LitePCIeMSI()
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if msi_type == "msi-multi-vector":
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msi = LitePCIeMSIMultiVector()
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if msi_type == "msi-x":
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msi = LitePCIeMSIX(endpoint=self.pcie_endpoint)
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self.add_module(name=f"{name}_msi", module=msi)
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self.add_module(name=f"{name}_msi", module=msi)
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# FIXME: On Ultrascale/Ultrascale+ limit rate of IRQs to 1MHz (to prevent issue with
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# FIXME: On Ultrascale/Ultrascale+ limit rate of IRQs to 1MHz (to prevent issue with
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# IRQs stalled).
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# IRQs stalled).
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if msi_type in ["msi", "msi-multi-vector"]:
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if isinstance(phy, (USPCIEPHY, USPPCIEPHY)):
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if isinstance(phy, (USPCIEPHY, USPPCIEPHY)):
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msi_timer = WaitTimer(int(self.sys_clk_freq/1e6))
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msi_timer = WaitTimer(int(self.sys_clk_freq/1e6))
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self.add_module(name=f"{name}_msi_timer", module=msi_timer)
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self.add_module(name=f"{name}_msi_timer", module=msi_timer)
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