boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out
This commit is contained in:
Florent Kermarrec
parent
1425a68d9e
commit
a9d55b04c0
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@ -18,7 +18,7 @@ _io = [
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("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
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# flash
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# spiflash
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("flash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("mosi", Pins("P22")),
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@ -28,6 +28,13 @@ _io = [
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IOStandard("LVCMOS33")
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),
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# spiflash4x
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("dq", Pins("P22 R22 P21 R21")),
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IOStandard("LVCMOS33")
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),
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# serial
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("serial", 0,
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Subsignal("tx", Pins("E14")),
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@ -39,28 +46,28 @@ _io = [
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("ddram", 0,
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Subsignal("a", Pins(
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"U6 V4 W5 V5 AA1 Y2 AB1 AB3",
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"AB2 Y3 W6 Y1 V2 AA3"
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),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")),
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"AB2 Y3 W6 Y1 V2 AA3"),
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IOStandard("SSTL15_R")),
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Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")),
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Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15_R")),
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Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15_R")),
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Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")),
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Subsignal("dm", Pins("G1 H4 M5 L3"), IOStandard("SSTL15_R")),
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Subsignal("dq", Pins(
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"N2 M6 P1 N5 P2 N4 R1 P6 "
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"K3 M2 K4 M3 J6 L5 J4 K6 "
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),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("W9"), IOStandard("SSTL15")),
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"C2 F1 B1 F3 A1 D2 B2 E2",
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"J5 H3 K1 H2 J1 G2 H5 G3",
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"N2 M6 P1 N5 P2 N4 R1 P6",
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"K3 M2 K4 M3 J6 L5 J4 K6"),
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IOStandard("SSTL15_R"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("E1 K2 P5 M1"), IOStandard("DIFF_SSTL15_R")),
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Subsignal("dqs_n", Pins("D1 J2 P4 L1"), IOStandard("DIFF_SSTL15_R")),
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Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15_R")),
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Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15_R")),
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Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")),
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Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")),
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Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
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Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15_R")),
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Misc("SLEW=FAST"),
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),
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@ -90,6 +97,57 @@ _io = [
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Subsignal("clk", Pins("K18")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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# hdmi in
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data0_p", Pins("K21"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data0_n", Pins("K22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data1_p", Pins("J20"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data1_n", Pins("J21"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data2_p", Pins("J22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data2_n", Pins("H22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("scl", Pins("T18"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("V18"), IOStandard("LVCMOS33")),
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),
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("hdmi_in", 1,
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Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data0_p", Pins("AA18"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("AB18"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("AA19"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data1_n", Pins("AB20"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data2_p", Pins("AB21"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data2_n", Pins("AB22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("scl", Pins("W17"), IOStandard("LVCMOS33"), Inverted()),
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Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")),
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),
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# hdmi out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("W19"), Inverted(), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("W20"), Inverted(), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("W21"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W22"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("U20"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("V20"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("T21"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("U21"), IOStandard("TMDS_33"))
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),
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("hdmi_out", 1,
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Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data0_p", Pins("E22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data0_n", Pins("D22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data1_p", Pins("C22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data1_n", Pins("B22"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data2_p", Pins("B21"), IOStandard("TMDS_33"), Inverted()),
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Subsignal("data2_n", Pins("A21"), IOStandard("TMDS_33"), Inverted()),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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@ -27,6 +27,7 @@ class _CRG(Module):
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk100 = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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@ -41,6 +42,7 @@ class _CRG(Module):
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk100, 100e6)
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pll.create_clkout(self.cd_eth, 50e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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