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udpip_tb: able to send valid UDP msg to model

This commit is contained in:
Florent Kermarrec 2015-02-04 22:15:59 +01:00
parent 4e5bd46f2d
commit a9da9dc750
4 changed files with 21 additions and 22 deletions
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5
liteeth/core/ip.py
View File

@ -49,7 +49,7 @@ class LiteEthIPTX(Module):
packetizer.sink.stb.eq(self.sink.stb),
packetizer.sink.sop.eq(self.sink.sop),
packetizer.sink.eop.eq(self.sink.eop),
self.sink.eq(packetizer.sink.ack),
self.sink.ack.eq(packetizer.sink.ack),
packetizer.sink.destination_ip_address.eq(ip_address),
packetizer.sink.protocol.eq(self.sink.protocol),
packetizer.sink.total_length.eq(self.sink.length + (0x5*4)),
@ -61,7 +61,8 @@ class LiteEthIPTX(Module):
packetizer.sink.flags.eq(0),
packetizer.sink.fragment_offset.eq(0),
packetizer.sink.time_to_live.eq(0x80),
packetizer.sink.source_ip_address.eq(ip_address)
packetizer.sink.source_ip_address.eq(ip_address),
packetizer.sink.data.eq(self.sink.data)
]
sink = packetizer.source

3
liteeth/core/udp.py
View File

@ -29,11 +29,12 @@ class LiteEthUDPTX(Module):
packetizer.sink.stb.eq(self.sink.stb),
packetizer.sink.sop.eq(self.sink.sop),
packetizer.sink.eop.eq(self.sink.eop),
self.sink.eq(packetizer.sink.ack),
self.sink.ack.eq(packetizer.sink.ack),
packetizer.sink.source_port.eq(self.sink.source_port),
packetizer.sink.destination_port.eq(self.sink.destination_port),
packetizer.sink.length.eq(self.sink.length + udp_header_len),
packetizer.sink.checksum.eq(0),
packetizer.sink.data.eq(self.sink.data)
]
sink = packetizer.source

2
liteeth/test/common.py
View File

@ -72,7 +72,7 @@ class Packet(list):
self.append(data)
class PacketStreamer(Module):
def __init__(self, description, last_be=1):
def __init__(self, description, last_be=None):
self.source = Source(description)
self.last_be = last_be
###

33
liteeth/test/udpip_tb.py
View File

@ -14,13 +14,21 @@ mac_address = 0x12345678abcd
class TB(Module):
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=True)
self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
self.submodules.phy_model = phy.PHY(8, debug=True)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=True, loopback=False)
self.submodules.udp_ip = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address)
self.submodules.streamer = PacketStreamer(eth_udp_user_description(8))
self.comb += [
Record.connect(self.streamer.source, self.udp_ip.sink),
self.udp_ip.sink.ip_address.eq(0x12345678),
self.udp_ip.sink.source_port.eq(0x1234),
self.udp_ip.sink.destination_port.eq(0x5678),
self.udp_ip.sink.length.eq(64)
]
# use sys_clk for each clock_domain
self.clock_domains.cd_eth_rx = ClockDomain()
@ -43,19 +51,8 @@ class TB(Module):
yield
while True:
selfp.udp_ip.sink.stb = 1
selfp.udp_ip.sink.sop = 1
selfp.udp_ip.sink.eop = 1
selfp.udp_ip.sink.ip_address = 0x12345678
selfp.udp_ip.sink.source_port = 0x1234
selfp.udp_ip.sink.destination_port = 0x5678
selfp.udp_ip.sink.length = 64
selfp.udp_ip.source.ack = 1
if selfp.udp_ip.source.stb == 1 and selfp.udp_ip.source.sop == 1:
print("IP Packet / from ip_address %08x" %selfp.udp_ip.sink.source_port)
yield
packet = Packet([i for i in range(64)])
yield from self.streamer.send(packet)
if __name__ == "__main__":
run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)