build/sim/common: Add SimAsyncResetSynchronizerImpl.
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@ -1,8 +1,26 @@
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from migen import *
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from migen import *
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from migen.fhdl.specials import Special
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from migen.fhdl.specials import Special
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import *
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from litex.build.io import *
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# AsyncResetSynchronizer ---------------------------------------------------------------------
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class SimAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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self.clock_domains.cd_resync = ClockDomain(reset_less=True)
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self.comb += self.cd_resync.clk.eq(cd.clk)
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rst1 = Signal()
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self.sync.resync += [
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rst1.eq(async_reset),
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cd.rst.eq(async_reset | rst1)
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]
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class SimAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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return SimAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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# DDROutput ----------------------------------------------------------------------------------------
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# DDROutput ----------------------------------------------------------------------------------------
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class SimDDROutputImpl(Module):
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class SimDDROutputImpl(Module):
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@ -38,6 +56,7 @@ class SimDDRInput:
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# Special Overrides --------------------------------------------------------------------------------
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# Special Overrides --------------------------------------------------------------------------------
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sim_special_overrides = {
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sim_special_overrides = {
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DDROutput: SimDDROutput,
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AsyncResetSynchronizer : SimAsyncResetSynchronizer,
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DDRInput: SimDDRInput,
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DDROutput : SimDDROutput,
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DDRInput : SimDDRInput,
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}
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}
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@ -268,7 +268,7 @@ class ClockDomainCrossing(Module):
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cd_to = "to"
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cd_to = "to"
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# Use common Rst on both Clk Domains (through AsyncResetSynchronizer).
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# Use common Rst on both Clk Domains (through AsyncResetSynchronizer).
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self.specials += [
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self.specials += [
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AsyncResetSynchronizer(_cd_from, _cd_rst),
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AsyncResetSynchronizer(_cd_from, _cd_rst),
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AsyncResetSynchronizer(_cd_to, _cd_rst),
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AsyncResetSynchronizer(_cd_to, _cd_rst),
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]
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]
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