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soc/cores/cpu/vexriscv_smp integration
This commit is contained in:
Dolu1990
parent
f87513ab92
commit
aa57c7a25e
9 changed files with 569 additions and 0 deletions
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@ -70,6 +70,7 @@ from litex.soc.cores.cpu.serv import SERV
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from litex.soc.cores.cpu.picorv32 import PicoRV32
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from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.vexriscv import VexRiscv
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from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
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from litex.soc.cores.cpu.cv32e40p import CV32E40P
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# RISC-V (64-bit)
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@ -98,6 +99,7 @@ CPUS = {
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"picorv32" : PicoRV32,
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"minerva" : Minerva,
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"vexriscv" : VexRiscv,
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"vexriscv_smp": VexRiscvSMP,
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"cv32e40p" : CV32E40P,
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# RISC-V (64-bit)
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1
litex/soc/cores/cpu/vexriscv_smp/__init__.py
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1
litex/soc/cores/cpu/vexriscv_smp/__init__.py
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@ -0,0 +1 @@
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from litex.soc.cores.cpu.vexriscv_smp.core import VexRiscvSMP
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29
litex/soc/cores/cpu/vexriscv_smp/boot-helper.S
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29
litex/soc/cores/cpu/vexriscv_smp/boot-helper.S
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@ -0,0 +1,29 @@
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.section .text, "ax", @progbits
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.global boot_helper
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.global smp_lottery_target
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.global smp_lottery_lock
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.global smp_lottery_args
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.global smp_slave
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boot_helper:
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sw x10, smp_lottery_args , x14
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sw x11, smp_lottery_args+4, x14
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sw x12, smp_lottery_args+8, x14
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sw x13, smp_lottery_target, x14
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fence w, w
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li x15, 1
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sw x15, smp_lottery_lock, x14
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jr x13
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smp_slave:
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lw a0, smp_lottery_lock
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beqz a0, smp_slave
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fence r, r
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.word(0x100F) //i$ flush
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lw x10, smp_lottery_args
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lw x11, smp_lottery_args+4
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lw x12, smp_lottery_args+8
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lw x13, smp_lottery_target
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jr x13
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317
litex/soc/cores/cpu/vexriscv_smp/core.py
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317
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -0,0 +1,317 @@
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
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# License: BSD
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import os
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from os import path
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from litex import get_data_mod
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from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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from litedram.common import LiteDRAMNativePort
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import os
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import os.path
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CPU_VARIANTS = {
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"linux": "VexRiscv",
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}
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class Open(Signal): pass
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class VexRiscvSMP(CPU):
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name = "vexriscv"
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human_name = "VexRiscv SMP"
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variants = CPU_VARIANTS
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data_width = 32
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV32
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linker_output_format = "elf32-littleriscv"
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nop = "nop"
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io_regions = {0x80000000: 0x80000000} # origin, length
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cpu_count = 1
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dcache_size = 8192
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icache_size = 8192
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dcache_ways = 2
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icache_ways = 2
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coherent_dma = False
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litedram_width = 128
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dbus_width = 64
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ibus_width = 64
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@staticmethod
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def args_fill(parser):
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parser.add_argument("--cpu-count", default=1, help="")
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parser.add_argument("--dcache-size", default=8192, help="")
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parser.add_argument("--dcache-ways", default=2, help="")
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parser.add_argument("--icache-size", default=8192, help="")
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parser.add_argument("--icache-ways", default=2, help="")
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@staticmethod
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def args_read(args):
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VexRiscvSMP.cpu_count = args.cpu_count
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VexRiscvSMP.dcache_size = args.dcache_size
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VexRiscvSMP.icache_size = args.icache_size
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VexRiscvSMP.dcache_ways = args.dcache_ways
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VexRiscvSMP.icache_ways = args.icache_ways
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@property
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def mem_map(self):
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return {
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"rom": 0x00000000,
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"sram": 0x10000000,
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"main_ram": 0x40000000,
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"csr": 0xf0000000,
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"clint": 0xf0010000,
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}
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@property
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def gcc_flags(self):
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flags = " -march=rv32ima -mabi=ilp32"
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flags += " -D__vexriscv__"
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flags += " -DUART_POLLING"
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return flags
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@staticmethod
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def generate_cluster_name():
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VexRiscvSMP.cluster_name = f"VexRiscvLitexSmpCluster_Cc{VexRiscvSMP.cpu_count}_Iw{VexRiscvSMP.ibus_width}Is{VexRiscvSMP.icache_size}Iy{VexRiscvSMP.icache_ways}_Dw{VexRiscvSMP.dbus_width}Ds{VexRiscvSMP.dcache_size}Dy{VexRiscvSMP.dcache_ways}_Ldw{VexRiscvSMP.litedram_width}{'_Cdma' if VexRiscvSMP.coherent_dma else ''}"
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@staticmethod
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def generate_default_configs():
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VexRiscvSMP.ibus_width = 64
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VexRiscvSMP.dbus_width = 64
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VexRiscvSMP.dcache_size = 8192
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VexRiscvSMP.icache_size = 8192
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VexRiscvSMP.dcache_ways = 2
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VexRiscvSMP.icache_ways = 2
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VexRiscvSMP.litedram_width = 128
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VexRiscvSMP.coherent_dma = True
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for core_count in [1,2,4]:
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VexRiscvSMP.cpu_count = core_count
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VexRiscvSMP.generate_cluster_name()
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VexRiscvSMP.generate_netlist()
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VexRiscvSMP.coherent_dma = False
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for core_count in [1]:
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VexRiscvSMP.cpu_count = core_count
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VexRiscvSMP.generate_cluster_name()
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VexRiscvSMP.generate_netlist()
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@staticmethod
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def generate_netlist():
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print(f"Generating cluster netlist")
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vdir = get_data_mod("cpu", "vexriscv_smp").data_location
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gen_args = []
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if(VexRiscvSMP.coherent_dma) : gen_args.append("--coherent-dma")
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gen_args.append(f"--cpu-count={VexRiscvSMP.cpu_count}")
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gen_args.append(f"--ibus-width={VexRiscvSMP.ibus_width}")
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gen_args.append(f"--dbus-width={VexRiscvSMP.dbus_width}")
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gen_args.append(f"--dcache-size={VexRiscvSMP.dcache_size}")
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gen_args.append(f"--icache-size={VexRiscvSMP.icache_size}")
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gen_args.append(f"--dcache-ways={VexRiscvSMP.dcache_ways}")
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gen_args.append(f"--icache-ways={VexRiscvSMP.icache_ways}")
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gen_args.append(f"--litedram-width={VexRiscvSMP.litedram_width}")
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gen_args.append(f"--netlist-name={VexRiscvSMP.cluster_name}")
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gen_args.append(f"--netlist-directory={vdir}")
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cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
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os.system(cmd)
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def __init__(self, platform, variant):
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self.platform = platform
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self.variant = "standard"
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self.human_name = self.human_name + "-" + variant.upper()
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self.reset = Signal()
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self.jtag_clk = Signal()
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self.jtag_enable = Signal()
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self.jtag_capture = Signal()
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self.jtag_shift = Signal()
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self.jtag_update = Signal()
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self.jtag_reset = Signal()
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self.jtag_tdo = Signal()
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self.jtag_tdi = Signal()
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self.interrupt = Signal(32)
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self.pbus = pbus = wishbone.Interface()
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self.cbus = cbus = wishbone.Interface()
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self.plicbus = plicbus = wishbone.Interface()
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self.periph_buses = [pbus]
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self.memory_buses = [] # Added dynamically
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VexRiscvSMP.generate_cluster_name()
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# # #
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self.cpu_params = dict(
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# Clk / Rst
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i_debugCd_external_clk = ClockSignal(),
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i_debugCd_external_reset = ResetSignal() | self.reset,
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# Interrupts
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i_interrupts = self.interrupt,
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# JTAG
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i_jtag_clk = self.jtag_clk,
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i_debugPort_enable = self.jtag_enable,
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i_debugPort_capture = self.jtag_capture,
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i_debugPort_shift = self.jtag_shift,
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i_debugPort_update = self.jtag_update,
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i_debugPort_reset = self.jtag_reset,
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i_debugPort_tdi = self.jtag_tdi,
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o_debugPort_tdo = self.jtag_tdo,
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# Peripheral Bus (Master)
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o_peripheral_CYC = pbus.cyc,
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o_peripheral_STB = pbus.stb,
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i_peripheral_ACK = pbus.ack,
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o_peripheral_WE = pbus.we,
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o_peripheral_ADR = pbus.adr,
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i_peripheral_DAT_MISO = pbus.dat_r,
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o_peripheral_DAT_MOSI = pbus.dat_w,
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o_peripheral_SEL = pbus.sel,
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i_peripheral_ERR = pbus.err,
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o_peripheral_CTI = pbus.cti,
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o_peripheral_BTE = pbus.bte,
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# CLINT Bus (Slave)
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i_clintWishbone_CYC = cbus.cyc,
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i_clintWishbone_STB = cbus.stb,
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o_clintWishbone_ACK = cbus.ack,
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i_clintWishbone_WE = cbus.we,
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i_clintWishbone_ADR = cbus.adr,
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o_clintWishbone_DAT_MISO = cbus.dat_r,
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i_clintWishbone_DAT_MOSI = cbus.dat_w,
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# PLIC Bus (Slave)
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i_plicWishbone_CYC = plicbus.cyc,
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i_plicWishbone_STB = plicbus.stb,
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o_plicWishbone_ACK = plicbus.ack,
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i_plicWishbone_WE = plicbus.we,
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i_plicWishbone_ADR = plicbus.adr,
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o_plicWishbone_DAT_MISO = plicbus.dat_r,
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i_plicWishbone_DAT_MOSI = plicbus.dat_w
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)
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if self.coherent_dma:
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self.dma_bus = dma_bus = wishbone.Interface(data_width=64)
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dma_bus_stall = Signal()
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dma_bus_inhibit = Signal()
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self.cpu_params.update(
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i_dma_wishbone_CYC = dma_bus.cyc,
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i_dma_wishbone_STB = dma_bus.stb & ~dma_bus_inhibit,
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o_dma_wishbone_ACK = dma_bus.ack,
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i_dma_wishbone_WE = dma_bus.we,
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i_dma_wishbone_SEL = dma_bus.sel,
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i_dma_wishbone_ADR = dma_bus.adr,
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o_dma_wishbone_DAT_MISO = dma_bus.dat_r,
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i_dma_wishbone_DAT_MOSI = dma_bus.dat_w,
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o_dma_wishbone_STALL = dma_bus_stall
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)
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self.sync += [
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If(dma_bus.stb & dma_bus.cyc & ~dma_bus_stall,
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dma_bus_inhibit.eq(1),
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),
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If(dma_bus.ack,
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dma_bus_inhibit.eq(0)
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)
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]
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if "mp" in variant:
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ncpus = int(variant[-2]) # FIXME
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for n in range(ncpus):
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ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=128)
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dbus = LiteDRAMNativePort(mode="both", address_width=32, data_width=128)
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self.memory_buses.append(ibus)
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self.memory_buses.append(dbus)
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self.cpu_params.update({
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# Instruction Memory Bus (Master)
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"o_io_iMem_{}_cmd_valid".format(n) : ibus.cmd.valid,
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"i_io_iMem_{}_cmd_ready".format(n) : ibus.cmd.ready,
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"o_io_iMem_{}_cmd_payload_we".format(n) : ibus.cmd.we,
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"o_io_iMem_{}_cmd_payload_addr".format(n) : ibus.cmd.addr,
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"o_io_iMem_{}_wdata_valid".format(n) : ibus.wdata.valid,
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"i_io_iMem_{}_wdata_ready".format(n) : ibus.wdata.ready,
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"o_io_iMem_{}_wdata_payload_data".format(n) : ibus.wdata.data,
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"o_io_iMem_{}_wdata_payload_we".format(n) : ibus.wdata.we,
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"i_io_iMem_{}_rdata_valid".format(n) : ibus.rdata.valid,
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"o_io_iMem_{}_rdata_ready".format(n) : ibus.rdata.ready,
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"i_io_iMem_{}_rdata_payload_data".format(n) : ibus.rdata.data,
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# Data Memory Bus (Master)
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"o_io_dMem_{}_cmd_valid".format(n) : dbus.cmd.valid,
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"i_io_dMem_{}_cmd_ready".format(n) : dbus.cmd.ready,
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"o_io_dMem_{}_cmd_payload_we".format(n) : dbus.cmd.we,
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"o_io_dMem_{}_cmd_payload_addr".format(n) : dbus.cmd.addr,
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"o_io_dMem_{}_wdata_valid".format(n) : dbus.wdata.valid,
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"i_io_dMem_{}_wdata_ready".format(n) : dbus.wdata.ready,
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"o_io_dMem_{}_wdata_payload_data".format(n) : dbus.wdata.data,
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"o_io_dMem_{}_wdata_payload_we".format(n) : dbus.wdata.we,
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"i_io_dMem_{}_rdata_valid".format(n) : dbus.rdata.valid,
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"o_io_dMem_{}_rdata_ready".format(n) : dbus.rdata.ready,
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"i_io_dMem_{}_rdata_payload_data".format(n) : dbus.rdata.data,
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})
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else:
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ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=128)
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dbus = LiteDRAMNativePort(mode="both", address_width=32, data_width=128)
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self.memory_buses.append(ibus)
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self.memory_buses.append(dbus)
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self.cpu_params.update(
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# Instruction Memory Bus (Master)
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o_iBridge_dram_cmd_valid = ibus.cmd.valid,
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i_iBridge_dram_cmd_ready = ibus.cmd.ready,
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o_iBridge_dram_cmd_payload_we = ibus.cmd.we,
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o_iBridge_dram_cmd_payload_addr = ibus.cmd.addr,
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o_iBridge_dram_wdata_valid = ibus.wdata.valid,
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i_iBridge_dram_wdata_ready = ibus.wdata.ready,
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o_iBridge_dram_wdata_payload_data = ibus.wdata.data,
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o_iBridge_dram_wdata_payload_we = ibus.wdata.we,
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i_iBridge_dram_rdata_valid = ibus.rdata.valid,
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o_iBridge_dram_rdata_ready = ibus.rdata.ready,
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i_iBridge_dram_rdata_payload_data = ibus.rdata.data,
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# Data Memory Bus (Master)
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o_dBridge_dram_cmd_valid = dbus.cmd.valid,
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i_dBridge_dram_cmd_ready = dbus.cmd.ready,
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o_dBridge_dram_cmd_payload_we = dbus.cmd.we,
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o_dBridge_dram_cmd_payload_addr = dbus.cmd.addr,
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o_dBridge_dram_wdata_valid = dbus.wdata.valid,
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i_dBridge_dram_wdata_ready = dbus.wdata.ready,
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o_dBridge_dram_wdata_payload_data = dbus.wdata.data,
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o_dBridge_dram_wdata_payload_we = dbus.wdata.we,
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i_dBridge_dram_rdata_valid = dbus.rdata.valid,
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o_dBridge_dram_rdata_ready = dbus.rdata.ready,
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i_dBridge_dram_rdata_payload_data = dbus.rdata.data,
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)
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# Add verilog sources
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self.add_sources(platform, variant)
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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assert reset_address == 0x00000000
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def add_sources(self, platform, variant):
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vdir = get_data_mod("cpu", "vexriscv_smp").data_location
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print(f"VexRiscv cluster : {self.cluster_name}")
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if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
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self.generate_netlist()
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platform.add_source(os.path.join(vdir, "RamXilinx.v"), "verilog")
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platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance(self.cluster_name, **self.cpu_params)
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107
litex/soc/cores/cpu/vexriscv_smp/crt0.S
Normal file
107
litex/soc/cores/cpu/vexriscv_smp/crt0.S
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
.global main
|
||||
.global isr
|
||||
.global _start
|
||||
|
||||
.global smp_lottery_target
|
||||
.global smp_lottery_lock
|
||||
.global smp_lottery_args
|
||||
.global smp_slave
|
||||
|
||||
_start:
|
||||
j crt_init
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
sw x1, - 1*4(sp)
|
||||
sw x5, - 2*4(sp)
|
||||
sw x6, - 3*4(sp)
|
||||
sw x7, - 4*4(sp)
|
||||
sw x10, - 5*4(sp)
|
||||
sw x11, - 6*4(sp)
|
||||
sw x12, - 7*4(sp)
|
||||
sw x13, - 8*4(sp)
|
||||
sw x14, - 9*4(sp)
|
||||
sw x15, -10*4(sp)
|
||||
sw x16, -11*4(sp)
|
||||
sw x17, -12*4(sp)
|
||||
sw x28, -13*4(sp)
|
||||
sw x29, -14*4(sp)
|
||||
sw x30, -15*4(sp)
|
||||
sw x31, -16*4(sp)
|
||||
addi sp,sp,-16*4
|
||||
call isr
|
||||
lw x1 , 15*4(sp)
|
||||
lw x5, 14*4(sp)
|
||||
lw x6, 13*4(sp)
|
||||
lw x7, 12*4(sp)
|
||||
lw x10, 11*4(sp)
|
||||
lw x11, 10*4(sp)
|
||||
lw x12, 9*4(sp)
|
||||
lw x13, 8*4(sp)
|
||||
lw x14, 7*4(sp)
|
||||
lw x15, 6*4(sp)
|
||||
lw x16, 5*4(sp)
|
||||
lw x17, 4*4(sp)
|
||||
lw x28, 3*4(sp)
|
||||
lw x29, 2*4(sp)
|
||||
lw x30, 1*4(sp)
|
||||
lw x31, 0*4(sp)
|
||||
addi sp,sp,16*4
|
||||
mret
|
||||
.text
|
||||
|
||||
crt_init:
|
||||
la sp, _fstack + 4
|
||||
la a0, trap_entry
|
||||
csrw mtvec, a0
|
||||
sw x0, smp_lottery_lock, a1
|
||||
|
||||
data_init:
|
||||
la a0, _fdata
|
||||
la a1, _edata
|
||||
la a2, _fdata_rom
|
||||
data_loop:
|
||||
beq a0,a1,data_done
|
||||
lw a3,0(a2)
|
||||
sw a3,0(a0)
|
||||
add a0,a0,4
|
||||
add a2,a2,4
|
||||
j data_loop
|
||||
data_done:
|
||||
|
||||
smp_tyranny:
|
||||
csrr a0, mhartid
|
||||
beqz a0, bss_init
|
||||
call smp_slave
|
||||
|
||||
|
||||
|
||||
bss_init:
|
||||
la a0, _fbss
|
||||
la a1, _ebss
|
||||
bss_loop:
|
||||
beq a0,a1,bss_done
|
||||
sw zero,0(a0)
|
||||
add a0,a0,4
|
||||
j bss_loop
|
||||
bss_done:
|
||||
|
||||
call main
|
||||
infinit_loop:
|
||||
j infinit_loop
|
||||
|
||||
|
||||
|
||||
//Initialized to avoid having them set to zero by BSS clear
|
||||
.bss
|
||||
smp_lottery_target: .word 0
|
||||
smp_lottery_args: .word 0; .word 0; .word 0
|
||||
smp_lottery_lock: .word 0
|
||||
|
||||
11
litex/soc/cores/cpu/vexriscv_smp/csr-defs.h
Normal file
11
litex/soc/cores/cpu/vexriscv_smp/csr-defs.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef CSR_DEFS__H
|
||||
#define CSR_DEFS__H
|
||||
|
||||
#define CSR_MSTATUS_MIE 0x8
|
||||
|
||||
#define CSR_IRQ_MASK 0xBC0
|
||||
#define CSR_IRQ_PENDING 0xFC0
|
||||
|
||||
#define CSR_DCACHE_INFO 0xCC0
|
||||
|
||||
#endif /* CSR_DEFS__H */
|
||||
42
litex/soc/cores/cpu/vexriscv_smp/irq.h
Normal file
42
litex/soc/cores/cpu/vexriscv_smp/irq.h
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
#ifndef __IRQ_H
|
||||
#define __IRQ_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <system.h>
|
||||
#include <generated/csr.h>
|
||||
#include <generated/soc.h>
|
||||
|
||||
static inline unsigned int irq_getie(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void irq_setie(unsigned int ie)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static inline unsigned int irq_getmask(void)
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void irq_setmask(unsigned int mask)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static inline unsigned int irq_pending(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IRQ_H */
|
||||
59
litex/soc/cores/cpu/vexriscv_smp/system.h
Normal file
59
litex/soc/cores/cpu/vexriscv_smp/system.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
#ifndef __SYSTEM_H
|
||||
#define __SYSTEM_H
|
||||
|
||||
#include <csr-defs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
__attribute__((unused)) static void flush_cpu_icache(void)
|
||||
{
|
||||
asm volatile(
|
||||
".word(0x100F)\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
"nop\n"
|
||||
);
|
||||
}
|
||||
|
||||
__attribute__((unused)) static void flush_cpu_dcache(void)
|
||||
{
|
||||
asm volatile(".word(0x500F)\n");
|
||||
}
|
||||
|
||||
void flush_l2_cache(void);
|
||||
|
||||
void busy_wait(unsigned int ms);
|
||||
|
||||
#include <csr-defs.h>
|
||||
|
||||
#define csrr(reg) ({ unsigned long __tmp; \
|
||||
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
|
||||
#define csrw(reg, val) ({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
|
||||
|
||||
#define csrs(reg, bit) ({ \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
|
||||
|
||||
#define csrc(reg, bit) ({ \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_H */
|
||||
|
|
@ -46,6 +46,7 @@ repos = [
|
|||
("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-serv", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-vexriscv_smp",("https://github.com/litex-hub/", True, True, None)),
|
||||
("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True, 0xba76652)),
|
||||
|
|
|
|||
Loading…
Reference in a new issue