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integration/soc: Add CSR automatic allocation and enable it by default. 

Un-allocated CSRs were already automatically detected so when un-allocated we can just
simply allocate them automatically instead of raising an error. This also allows
simplifying user's code since self.csr.add/self.add_csr will no longer be required.
This commit is contained in:
Florent Kermarrec 2021-03-25 09:49:59 +01:00
parent 3def6ae985
commit aa9eb1f6a3
1 changed files with 25 additions and 16 deletions
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31
litex/soc/integration/soc.py
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@ -587,10 +587,18 @@ class SoCCSRHandler(SoCLocHandler):
self.regions[name] = region self.regions[name] = region
# Address map ---------------------------------------------------------------------------------- # Address map ----------------------------------------------------------------------------------
def address_map(self, name, memory): def address_map(self, name, memory, auto_alloc=True):
if memory is not None: if memory is not None:
name = name + "_" + memory.name_override name = name + "_" + memory.name_override
if self.locs.get(name, None) is None: if self.locs.get(name, None) is None:
if auto_alloc:
self.add(name, use_loc_if_exists=True)
else:
self.logger.info("{} {} {} at Location {}.".format(
colorer(name, color="underline"),
self.name,
colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
colorer(n)))
self.logger.error("CSR {} {}.".format( self.logger.error("CSR {} {}.".format(
colorer(name), colorer(name),
colorer("not found", color="red"))) colorer("not found", color="red")))
@ -930,16 +938,6 @@ class SoC(Module):
# SoC finalization ----------------------------------------------------------------------------- # SoC finalization -----------------------------------------------------------------------------
def do_finalize(self): def do_finalize(self):
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Finalized SoC:"))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(self.bus)
if hasattr(self, "dma_bus"):
self.logger.info(self.dma_bus)
self.logger.info(self.csr)
self.logger.info(self.irq)
self.logger.info(colorer("-"*80, color="bright"))
interconnect_p2p_cls = { interconnect_p2p_cls = {
"wishbone": wishbone.InterconnectPointToPoint, "wishbone": wishbone.InterconnectPointToPoint,
"axi-lite": axi.AXILiteInterconnectPointToPoint, "axi-lite": axi.AXILiteInterconnectPointToPoint,
@ -1082,6 +1080,17 @@ class SoC(Module):
self.comb += self.cpu.interrupt[loc].eq(module.ev.irq) self.comb += self.cpu.interrupt[loc].eq(module.ev.irq)
self.add_constant(name + "_INTERRUPT", loc) self.add_constant(name + "_INTERRUPT", loc)
# SoC Infos --------------------------------------------------------------------------------
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Finalized SoC:"))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(self.bus)
if hasattr(self, "dma_bus"):
self.logger.info(self.dma_bus)
self.logger.info(self.csr)
self.logger.info(self.irq)
self.logger.info(colorer("-"*80, color="bright"))
# SoC build ------------------------------------------------------------------------------------ # SoC build ------------------------------------------------------------------------------------
def build(self, *args, **kwargs): def build(self, *args, **kwargs):
self.build_name = kwargs.pop("build_name", self.platform.name) self.build_name = kwargs.pop("build_name", self.platform.name)