soc/cores/jtag: adding Efinix JTAG support in JTAGPHY

litex/soc/cores/jtag.py

@@ -426,6 +426,9 @@ class JTAGPHY(LiteXModule):
             # Lattice.
             elif device[:5] == "LFE5U":
                 jtag = ECP5JTAG()
+            # Efinix
+            elif device[:2] == "Ti":
+                jtag = EfinixJTAG(platform)
             # Altera/Intel.
             elif AlteraJTAG.get_primitive(device) is not None:
                 platform.add_reserved_jtag_decls()
@@ -511,6 +514,16 @@ class JTAGPHY(LiteXModule):
 class EfinixJTAG(LiteXModule):
     # id refer to the JTAG_USER{id}
     def __init__(self, platform, id=1):
+        self.reset   = Signal()
+        self.capture = Signal()
+        self.shift   = Signal()
+        self.update  = Signal()
+
+        self.tck = Signal()
+        self.tms = Signal()
+        self.tdi = Signal()
+        self.tdo = Signal()
+
         self.name     = f"jtag_{id}"
         self.platform = platform
         self.id       = id
@@ -543,6 +556,18 @@ class EfinixJTAG(LiteXModule):
         block["pins"] = pins
         self.platform.toolchain.ifacewriter.blocks.append(block)
 
+        self.comb += [
+            self.reset.eq(pins.RESET),
+            self.capture.eq(pins.CAPTURE),
+            self.shift.eq(pins.SHIFT),
+            self.update.eq(pins.UPDATE),
+
+            self.tck.eq(pins.TCK),
+            self.tms.eq(pins.TMS),
+            self.tdi.eq(pins.TDI),
+            pins.TDO.eq(self.tdo),
+        ]
+
     def bind_vexriscv_smp(self, cpu):
         self.comb += [
             # JTAG -> CPU.