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Merge pull request #22 from mithro/master 

soc_core: Add CPU_RESET_ADDR as a constant.
This commit is contained in:
enjoy-digital 2017-03-12 13:53:27 +01:00 committed by GitHub
parent c69012d713 4ee7019852
commit ab075f3d80
1 changed files with 3 additions and 2 deletions
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5
litex/soc/integration/soc_core.py
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@ -44,6 +44,8 @@ class SoCCore(Module):
with_uart=True, uart_baudrate=115200, with_uart=True, uart_baudrate=115200,
ident="", ident="",
with_timer=True): with_timer=True):
self.config = dict()
self.platform = platform self.platform = platform
self.clk_freq = clk_freq self.clk_freq = clk_freq
@ -51,6 +53,7 @@ class SoCCore(Module):
if integrated_rom_size: if integrated_rom_size:
cpu_reset_address = self.mem_map["rom"] cpu_reset_address = self.mem_map["rom"]
self.cpu_reset_address = cpu_reset_address self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size self.integrated_sram_size = integrated_sram_size
@ -71,8 +74,6 @@ class SoCCore(Module):
self._wb_masters = [] self._wb_masters = []
self._wb_slaves = [] self._wb_slaves = []
self.config = dict()
if cpu_type is not None: if cpu_type is not None:
if cpu_type == "lm32": if cpu_type == "lm32":
self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address)) self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address))