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litex/tools: add command line options and fixes for lxterm to allow crossover uart over PCIe

This commit is contained in:
Nathaniel R. Lewis 2021-09-07 19:17:50 -07:00
parent e0e9311ceb
commit ab3d7e86f2
2 changed files with 26 additions and 13 deletions
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5
litex/tools/litex_client.py
View File

@ -31,8 +31,11 @@ class RemoteClient(EtherboneIPC, CSRBuilder):
csr_data_width = 32 csr_data_width = 32
self.host = host self.host = host
self.port = port self.port = port
self.base_address = base_address
self.debug = debug self.debug = debug
if base_address is not None:
self.base_address = base_address
else:
self.base_address = 0
def open(self): def open(self):
if hasattr(self, "socket"): if hasattr(self, "socket"):

16
litex/tools/litex_term.py
View File

@ -87,8 +87,8 @@ else:
from litex import RemoteClient from litex import RemoteClient
class BridgeUART: class BridgeUART:
def __init__(self, name="uart_xover", host="localhost", base_address=0): # FIXME: add command line arguments def __init__(self, name="uart_xover", host="localhost", base_address=None, csr_csv=None): # FIXME: add command line arguments
self.bus = RemoteClient(host=host, base_address=base_address) self.bus = RemoteClient(host=host, base_address=base_address, csr_csv=csr_csv)
present = False present = False
for k, v in self.bus.regs.d.items(): for k, v in self.bus.regs.d.items():
if f"{name}_" in k: if f"{name}_" in k:
@ -97,6 +97,10 @@ class BridgeUART:
if not present: if not present:
raise ValueError(f"CrossoverUART {name} not present in design.") raise ValueError(f"CrossoverUART {name} not present in design.")
# On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
if base_address is None and hasattr(self.bus.bases, "pcie_phy"):
self.bus.base_address = -self.bus.mems.csr.base
def open(self): def open(self):
self.bus.open() self.bus.open()
self.file, self.name = pty.openpty() self.file, self.name = pty.openpty()
@ -540,6 +544,8 @@ def _get_args():
parser.add_argument("--kernel-adr", default="0x40000000", help="Kernel address") parser.add_argument("--kernel-adr", default="0x40000000", help="Kernel address")
parser.add_argument("--images", default=None, help="JSON description of the images to load to memory") parser.add_argument("--images", default=None, help="JSON description of the images to load to memory")
parser.add_argument("--csr-csv", default=None, help="SoC mapping file")
parser.add_argument("--base-address", default=None, help="CSR base address")
parser.add_argument("--bridge-name", default="uart_xover", help="Bridge UART name to use (present in design/csr.csv)") parser.add_argument("--bridge-name", default="uart_xover", help="Bridge UART name to use (present in design/csr.csv)")
parser.add_argument("--jtag-name", default="jtag_uart", help="JTAG UART type: jtag_uart (default), jtag_atlantic") parser.add_argument("--jtag-name", default="jtag_uart", help="JTAG UART type: jtag_uart (default), jtag_atlantic")
@ -555,7 +561,11 @@ def main():
if args.port in ["bridge", "jtag"]: if args.port in ["bridge", "jtag"]:
raise NotImplementedError raise NotImplementedError
if args.port in ["bridge", "crossover"]: # FIXME: 2021-02-18, crossover for retro-compatibility remove and update targets? if args.port in ["bridge", "crossover"]: # FIXME: 2021-02-18, crossover for retro-compatibility remove and update targets?
bridge = BridgeUART(name=args.bridge_name) if args.base_address is not None:
base_address = int(args.base_address)
else:
base_address = None
bridge = BridgeUART(base_address=base_address,csr_csv=args.csr_csv,name=args.bridge_name)
bridge.open() bridge.open()
port = os.ttyname(bridge.name) port = os.ttyname(bridge.name)
elif args.port in ["jtag"]: elif args.port in ["jtag"]: