soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.
This commit is contained in:
Florent Kermarrec
parent
0a3d649ad8
commit
ab80606036
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@ -4,14 +4,17 @@
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# This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
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# License: BSD
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from math import log2
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from migen import *
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from migen.genlib.record import Record
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr_eventmanager import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import stream
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from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
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# Common -------------------------------------------------------------------------------------------
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@ -239,10 +242,127 @@ class UART(Module, AutoCSR, UARTInterface):
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self.ev.rx.trigger.eq(~rx_fifo.source.valid)
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]
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class UARTBone(WishboneStreamingBridge):
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# UART Bone ----------------------------------------------------------------------------------------
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CMD_WRITE = 0x01
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CMD_READ = 0x02
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class Stream2Wishbone(Module):
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def __init__(self, phy, clk_freq, data_width=32, address_width=32):
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self.wishbone = wishbone.Interface()
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self.comb += phy.source.ready.eq(1) # Always accept incoming stream.
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# # #
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cmd = Signal(8, reset_less=True)
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length = Signal(8, reset_less=True)
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address = Signal(address_width, reset_less=True)
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data = Signal(data_width, reset_less=True)
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bytes_count = Signal(int(log2(data_width//8)), reset_less=True)
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words_count = Signal(8, reset_less=True)
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bytes_count_done = (bytes_count == (data_width//8 - 1))
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words_count_done = (words_count == (length - 1))
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fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
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timer = WaitTimer(int(100e-3*clk_freq))
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self.comb += timer.wait.eq(~fsm.ongoing("RECEIVE-CMD"))
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self.submodules += fsm, timer
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self.comb += fsm.reset.eq(timer.done)
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fsm.act("RECEIVE-CMD",
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NextValue(bytes_count, 0),
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NextValue(words_count, 0),
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If(phy.source.valid,
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NextValue(cmd, phy.source.data),
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NextState("RECEIVE-LENGTH")
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)
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)
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fsm.act("RECEIVE-LENGTH",
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If(phy.source.valid,
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NextValue(length, phy.source.data),
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NextState("RECEIVE-ADDRESS")
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)
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)
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fsm.act("RECEIVE-ADDRESS",
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If(phy.source.valid,
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NextValue(address, Cat(phy.source.data, address)),
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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If(cmd == CMD_WRITE,
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NextState("RECEIVE-DATA")
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).Elif(cmd == CMD_READ,
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NextState("READ-DATA")
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).Else(
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NextState("RECEIVE-CMD")
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)
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)
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)
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)
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fsm.act("RECEIVE-DATA",
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If(phy.source.valid,
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NextValue(data, Cat(phy.source.data, data)),
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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NextState("WRITE-DATA")
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)
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)
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)
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self.comb += [
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self.wishbone.adr.eq(address),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**(data_width//8) - 1)
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]
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fsm.act("WRITE-DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextValue(words_count, words_count + 1),
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NextValue(address, address + 1),
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If(words_count_done,
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NextState("RECEIVE-CMD")
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).Else(
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NextState("RECEIVE-DATA")
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)
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)
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)
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fsm.act("READ-DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextValue(data, self.wishbone.dat_r),
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NextState("SEND-DATA")
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)
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)
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cases = {}
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for i, n in enumerate(reversed(range(data_width//8))):
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cases[i] = phy.sink.data.eq(data[8*n:])
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self.comb += Case(bytes_count, cases)
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fsm.act("SEND-DATA",
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phy.sink.valid.eq(1),
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If(phy.sink.ready,
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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NextValue(words_count, words_count + 1),
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NextValue(address, address + 1),
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If(words_count_done,
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NextState("RECEIVE-CMD")
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).Else(
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NextState("READ-DATA")
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)
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)
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)
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)
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self.comb += phy.sink.last.eq(bytes_count_done & words_count_done)
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if hasattr(phy.sink, "length"):
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self.comb += phy.sink.length.eq((data_width//8)*length)
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class UARTBone(Stream2Wishbone):
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def __init__(self, pads, clk_freq, baudrate=115200):
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self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
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WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
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Stream2Wishbone.__init__(self, self.phy, clk_freq)
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class UARTWishboneBridge(UARTBone): pass
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@ -1,127 +0,0 @@
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from math import log2
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import stream
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# Wishbone Streaming Bridge ------------------------------------------------------------------------
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CMD_WRITE = 0x01
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CMD_READ = 0x02
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class WishboneStreamingBridge(Module):
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def __init__(self, phy, clk_freq, data_width=32, address_width=32):
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self.wishbone = wishbone.Interface()
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self.comb += phy.source.ready.eq(1) # Always accept incoming stream.
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# # #
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cmd = Signal(8, reset_less=True)
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length = Signal(8, reset_less=True)
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address = Signal(address_width, reset_less=True)
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data = Signal(data_width, reset_less=True)
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bytes_count = Signal(int(log2(data_width//8)), reset_less=True)
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words_count = Signal(8, reset_less=True)
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bytes_count_done = (bytes_count == (data_width//8 - 1))
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words_count_done = (words_count == (length - 1))
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fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
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timer = WaitTimer(int(100e-3*clk_freq))
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self.comb += timer.wait.eq(~fsm.ongoing("RECEIVE-CMD"))
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self.submodules += fsm, timer
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self.comb += fsm.reset.eq(timer.done)
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fsm.act("RECEIVE-CMD",
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NextValue(bytes_count, 0),
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NextValue(words_count, 0),
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If(phy.source.valid,
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NextValue(cmd, phy.source.data),
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NextState("RECEIVE-LENGTH")
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)
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)
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fsm.act("RECEIVE-LENGTH",
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If(phy.source.valid,
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NextValue(length, phy.source.data),
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NextState("RECEIVE-ADDRESS")
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)
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)
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fsm.act("RECEIVE-ADDRESS",
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If(phy.source.valid,
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NextValue(address, Cat(phy.source.data, address)),
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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If(cmd == CMD_WRITE,
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NextState("RECEIVE-DATA")
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).Elif(cmd == CMD_READ,
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NextState("READ-DATA")
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).Else(
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NextState("RECEIVE-CMD")
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)
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)
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)
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)
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fsm.act("RECEIVE-DATA",
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If(phy.source.valid,
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NextValue(data, Cat(phy.source.data, data)),
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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NextState("WRITE-DATA")
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)
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)
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)
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self.comb += [
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self.wishbone.adr.eq(address),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**(data_width//8) - 1)
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]
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fsm.act("WRITE-DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextValue(words_count, words_count + 1),
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NextValue(address, address + 1),
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If(words_count_done,
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NextState("RECEIVE-CMD")
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).Else(
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NextState("RECEIVE-DATA")
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)
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)
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)
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fsm.act("READ-DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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NextValue(data, self.wishbone.dat_r),
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NextState("SEND-DATA")
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)
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)
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cases = {}
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for i, n in enumerate(reversed(range(data_width//8))):
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cases[i] = phy.sink.data.eq(data[8*n:])
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self.comb += Case(bytes_count, cases)
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fsm.act("SEND-DATA",
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phy.sink.valid.eq(1),
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If(phy.sink.ready,
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NextValue(bytes_count, bytes_count + 1),
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If(bytes_count_done,
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NextValue(words_count, words_count + 1),
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NextValue(address, address + 1),
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If(words_count_done,
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NextState("RECEIVE-CMD")
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).Else(
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NextState("READ-DATA")
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)
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)
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)
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)
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self.comb += phy.sink.last.eq(bytes_count_done & words_count_done)
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if hasattr(phy.sink, "length"):
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self.comb += phy.sink.length.eq((data_width//8)*length)
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